ee141-spring 2006 digital integrated...

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EE141EE141--Spring 2006Spring 2006Digital Integrated Digital Integrated CircuitsCircuits

Lecture 16Lecture 16SRAM DesignSRAM Design

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AnnouncementsAnnouncements

Project launch todayPhase 1 due March 20

Homework #7 due next ThursdayNo new homework next week

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Midterm 1Midterm 1

Hi: 57Lo: 5Median: 30

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Midterm 1Midterm 1

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56+51-5546-5041-4536-4031-3526-3021-2516-2011-156-100-5

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Class MaterialClass Material

Last lectureDesign for speedMethod of logical effort

Today’s lectureSRAM design

Reading (Chapter 12)

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Logical Logical EffortEffort

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Optimum Effort per StageOptimum Effort per Stage

HhN =

When each stage bears the same effort:

N Hh =

( ) PNHpfgD Niii +=+= ∑ /1ˆ

Minimum path delay

Effective fanout of each stage: ii ghf =

Stage efforts: g1f1 = g2f2 = … = gNfN

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Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing

∑+= iN pNHD /1

NHh ˆ/1=The ‘best stage effort’

Remember: we can always add inverters to the end of the chain

is around 4 (3.6 with γ=1)

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Logical EffortLogical Effort

From Sutherland, Sproull

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Example: Optimize PathExample: Optimize Path

Effective fanout, F =G = H =h =a =b =

1a

b c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

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Example: Optimize PathExample: Optimize Path1

ab c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

Effective fanout, F = 5G = 25/9H = 125/9 = 13.9h = 1.93a = 1.93b = ha/g2 = 2.23c = hb/g3 = 5g4/f = 2.59

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Example Example –– 88--Input ANDInput AND

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Method of Logical EffortMethod of Logical EffortCompute the path effort: H = GBFFind the best number of stages N ~ log4HCompute the stage effort h = H1/N

Sketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/h

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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Semiconductor Semiconductor MemoryMemory

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ArrayArray--Structured Memory ArchitectureStructured Memory Architecture

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Semiconductor Memory ClassificationSemiconductor Memory Classification

Read-Write MemoryNon-VolatileRead-Write

MemoryRead-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

DRAM

Mask-Programmed

Programmable (PROM)

FIFO

Shift Register

CAM

LIFO

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ReadRead--Write Memories (RAM)Write Memories (RAM)STATIC (SRAM)

DYNAMIC (DRAM)

Data stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

Periodic refresh requiredSmall (1-3 transistors/cell)SlowerSingle Ended

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Positive Feedback: BiPositive Feedback: Bi--StabilityStabilityVi1 Vo2

Vo2 = Vi 1

Vo1 = Vi 2

V

o

1

V

i

2

5

V

o

1

V

i

2

5

V

o

1

Vi1

A

C

B

Vo2

Vi1 = Vo2

Vo1 Vi2

Vi2 = Vo1

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MetaMeta--StabilityStability

Gain should be larger than 1 in the transition region

A

C

δ

B

Vi2=

Vo1

Vi1 = Vo2

A

C

δ

B

Vi2

=V

o1

Vi1 = Vo2

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Writing into a CrossWriting into a Cross--Coupled PairCoupled Pair

Can implement as a transmission gate as wellAccess transistor must be able to overpower the feedback

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Memory CellMemory Cell

Complementary data values are written (read) from two sides

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66--transistor CMOS SRAM Cell transistor CMOS SRAM Cell

WL

BL

VDD

M5M6

M4

M1

M2

M3

BL

QQ