ee 319k introduction to embedded systems

15-1

EE 319KIntroduction to Embedded Systems

Lecture 15: Final Exam Review

Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

15-2

Final Exam

Final exam will be similar in style to Exam 1Approximately the same length and format as

previous final examsYou will have three hours if you need it

Comprehensive, good things to study are All the lecture notes & worksheets postedAll lab workTextbook (sections listed in syllabus)All homeworkZyante book (specified in HW)All prior exams (finals and Exam 1s)

o Time entire test alone; review solutions with friends

Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

15-3Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam

Any technical documents required will be provided Closed book, closed notes No calculators allowed (all calculations will be simple) Partial credit for answers in equation form http://users.ece.utexas.edu/~valvano/Volume1/FinalSp13a.pdf http://users.ece.utexas.edu/~valvano/Volume1/FinalF12a.pdf

It may have short answer questionsConversions, definitions

Will have longer questions involving assembly and CLocal variables, FSM, interrupts, ADC input, DACFocus will be on fundamentals and techniquesYou should be able to do software problems in

both assembly and C!

15-4Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review

Definitions (matching or multiple choice) volatile, nonvolatile, RAM, ROM, port, kibibyte, mebibyte static efficiency, dynamic efficiency, white box, black box structured program, call graph, data flow graph basis, nibble, precision, decimal digits, promotion, demotion fixed-point, overflow, ceiling and floor, drop out desk check, intrusive, dump, stabilization, profile, heartbeat bus, address bus, data bus, bus cycle memory-mapped, I/O mapped, vector, device driver, Von Neumann architecture, Harvard architecture, CISC, RISC tristate, open collector, ALU, registers negative logic, positive logic, Ohm’s Law, P=V*I, KVL, KCL thread, real-time, latency, interrupt, vector, priority private, public, local, global, call by value, call by reference friendly, mask, toggle, baud rate, bandwidth, frame Nyquist Theorem, monotonic, accuracy, jitter ADC/DAC limits: max, min, resolution, fs, number of samples PLL (tradeoff between power and speed)

15-5Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review

Number conversions - convert one format to another decimal digitssigned decimal e.g., -56unsigned decimal e.g., 200binary e.g., %11001000hexadecimal e.g., 0xC8IEEE 754 floating point (not this semester)

15-6Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review Instruction detail and Cortex-M operation

operation of ARM instructions (reference sheet) components in address space subroutine linkage stack operations 8-bit addition, subtraction yielding result, N, Z, V, C

o No N Z V C this semester

Simple programs create global variables specify an I/O pin is an input specify an I/O pin is an output clear an I/O output pin to zero set an I/O output pin to one toggle an I/O output pin check if an I/O input pin is high or low add, sub, shift left, shift right, and, or, eor subroutine linkage

15-7Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review

Switch & LED interfacing GPIO Ports

friendly programming practices LED and switch interfacing bit-specific addressing (no bit-specific addressing this year)

SysTick Timer initialization operational parameters

o period busy-wait delay or periodic interrupt

15-8Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review

System Design Successive Refinement, modularity Stepwise Refinement Systematic Decomposition

Finite State Machines Moore and Mealy machine characteristics abstraction programming structures

Local Variables types of storage

o stack, registers, binding, SP address, stack frame addressing C programming

Variables, expressions, control, data structures casting and indirection, pointers, arrays, structures storage type qualifiers

o const static volatile

15-9Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review I/O Synchronization

Purpose, typeso blind cycle, busy/wait, interrupt, DMAo Semaphore, mailbox, FIFO

Device Driver Performing I/O with an external device (like the LCD)

Interrupts initialization rituals

o software actions/what needs to be done interrupt service routines

o hardware operationo thread context switch/what needs to be done

debugging techniques Mailbox and FIFO queues

operation programming

But simpler

15-10Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Final Exam Review

Digital To Analog Converter (DAC) Operation, characteristics, Ohm’s Law

Sound Generation Discrete time sinusoid Periodic interrupts Timing requirements

Analog To Digital Converter (ADC) Operation, characteristics, programming Nyquist Theorem

UART Operation, programming, start bit, stop bit, rates

Real time and communication systems Latency, jitter, throughput ≡ bandwidth

15-11Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Practice Problems in Book

Hardware interfacing4.12, 4.13, 4.15, 4.17

Parallel Port initialization4.5, 4.6, 4.7, 4.10, 4.11

Software4.18, 4.19, 4.20, Lab 4.3, Lab 4.5, Lab 4.6,5.1, 5.2, 5.3, 5.4, 5.5, 5.6, 5.7, 5.8, 5.9, 5.10

15-12Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Practice Problems in Book

Pointers 6.1, 6.2, 6.3, 6.4, 6.6, 6.7, 6.9,

Matrix (2-D array) 6.10, 6.11,

FSM 6.12, 6.13, 6.14, 6.15

Variables 7.1, 7.2, 7.3, 7.4,

Parameters 7.5, 7.15, 7.16, 7.18

Fixed point 7.6, 7.7, 7.10, 7.11, 7.12, 7.13, 7.22

15-13Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Practice Problems in Book

Recursion 7.21

UART 8.1, 8.2, 8.3, 11.10, 11.11

SysTick, interrupts 9.1, 9.4, 9.7, 9.8, 9.10, 9.12, 9.15, 9.16

DAC 10.1 Checkpoints 10.1-10.7

ADC 10.2-10.11 Checkpoint 10.8

FIFO Checkpoints 11.2-11.5

15-14Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Comp Architecture/Embedded SystemsE

lect

ives

Ele

ctiv

es

EmbeddedSystems Lab

(EE 445L | FS)

Real-Timeand Embedded

Systems(EE 445M | S)

Real-TimeDSP

Laboratory(EE 445S | FS)

DigitalSystem Design

(EE 460M | FS)

ComputerArchitecture

(EE 460N | FS)

Introduction toMicrocontrollers

(EE 319K | FS)

Digital LogicDesign

(EE 316 | FS)

Algorithms

(EE 360C | FS)

Concurrent andDistributedSystems

(EE 360P | S)

Computer-AidedIC Design

(EE 460R | FS)

From small To large systems

Operating Systems (EE379K)

15-15Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Comp Architecture/Embedded Systems

Required EE 316 Digital Logic Design EE 460N Computer Architecture EE 445L Embedded Systems Lab EE 360C Algorithms M 325K Discrete Mathematics

Three of the following EE 422C Software Design and Implementation II EE 445M Embedded and Real-Time Systems Lab EE 445S Real-Time Digital Signal Processing Lab EE 460M Digital Systems Design Using VHDL EE 360P Concurrent and Distributed Systems EE 460R Computer-Aided Integrated Circuit Design EE 362K Introduction to Automatic Control CS 375 Compilers (Fall 2016 ECE course as

well) EE 379K New OS course, Fall 2015

15-16Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Computer System Design

Applications,Operating systems,Compilers,Instruction set, Microarchitecture, Logic design,Circuit design

Understanding the operation and design of computers

Good secondary cores: Electronics and IC, Software

15-17Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

We’ve Come a Long Way

Transistor count doubles every 18 months

15-18Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Computer Architecture Area

Design of general-purpose computer systemsFrom personal (laptops, desktops) to cloud (servers)

Which courses are most relevant & important?EE 460N for computer architecture

What are important technical challenges today?Size, speed, security, software/hardware, power

What industries/companies need these skills?Any company making computer equipment

How do I prepare for graduate school?Take EE 460N Comp. Arch. and EE 360C AlgorithmsGet involved in undergraduate researchMS degree is essential for this area

15-19Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

Embedded Systems Area

Design of special-purpose computer systemsFrom toasters (μController) to airplanes (systems-on-chip)

Which courses are most relevant & important?EE445L digital-analog codesign, systems level designEE445M real-time operating systems, device drivers,

and autonomous robots What are important technical challenges today?

Time-to-market; maximizing use of Moore’s lawSize, power, profit margins

What industries/companies need these skills?Any company making super high volume products

How do I prepare for graduate school?Take EE 460N Comp. Arch. and EE 360C AlgorithmsGet involved in undergraduate research

15-20Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE460N Computer Arch What is Architecture, Tradeoffs Instruction Set Architecture, LC-3b ISA Assemblers: Translating Assembly Language to ISA Microarchitecture: Detailed LC-3b implementation Physical memory, unaligned access, interleaving, SRAM, DRAM Virtual memory, page tables, TLB, VAX model, PowerPC model, contrast

with segmentation Cache memory Interrupts/Exceptions I/O Performance Improvement. Metrics, Pipelining. Branch prediction Out-of-order execution Vector processing Integer arithmetic, Floating point, IEEE Standard Measurement Methodology Intro to Multiprocessing, Interconnection networks, Amdahl's Law,

Consistency models Cache coherency Alternative Models of Concurrency: SIMD, MIMD, VLIW, dataflow, etc. State-of-the-art Microprocessor

15-21Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE460N - Labs

Write an assemblerWrite an instruction set simulatorWrite a cycle-level simulatorInterrupt supportVirtual memoryPipeline

15-22Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE460M Digital Design Using VHDL

Review of Basic Logic Design Techniques (with emphasis on timing)

Design Flow, High Level Design VHDL Descriptions of Digital Systems and Simulation Synthesis Design using Programmable Logic Devices SM Charts Field Programmable Gate Arrays (FPGAs) Advanced Topics in VHDL Test Generation and Design for Testability Rapid Prototyping using FPGAs

15-23Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE460M - Labs

VHDL’s timing to model gate-level circuits

FSM simulation VHDL Package Sorter Traffic Meter Simulation BCD conversion, Square Root Microprocessor Design & Implementation

in FPGA VGA Graphics and Keyboard Interface

15-24Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE445L Embedded Systems Lab

debugging with an oscilloscope and a logic analyzer; design of an alarm clock and I/O driver; design of a real-time data acquisition system; Motor control; design of a music player, DAC, data structure design; Power management and PCB layout; Wireless communication, layered protocol; board-level design, construction and testing of a

complete embedded system

15-25Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE445L - Labs

Lab 1. ASCII to fixed-point output to OLED Lab 2. Debugging, oscilloscope, logic analyzer, dump Lab 3. Alarm clock, edge-triggered input interrupts Lab 4. Stepper motor, interrupts, finite state machine Lab 5. 12-bit DAC, SPI, Music player, audio amp Lab 6. Introduction to PCB Layout, PCB Artist Lab 7. Design and Layout of an Embedded System Lab 8. Software Drivers for an Embedded System Lab 9. Measurement, ADC, analog amp Lab 10. Wifi, UART, distributed systems Lab 11. Evaluation of Embedded System

15-26Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

EE445M Real-time operating systems Lab 1. I/O port drivers Lab 2. Real-time operating system kernel Lab 3. Blocking semaphores, priority Lab 4. Microphone input, digital filters, FFT, Lab 5. Solid state disk, SSI, address translation,

layered software, file system Lab 6. Distributed acquisition using Ethernet Lab 7 Formula 0001 Racing Robot

Go watch the races in Spring

15-27Bard, Tiwari, Telang, Janapa Reddi, Gerstlauer, Valvano, Yerraballi

For more information Bard, Bill (network communications) Chase, Craig (software design) Chiou, Derek (architecture) Erez, Mattan (architecture) Evans, Brian L. (DSP applications) Gerstlauer, Andreas (embedded systems, IC) Janapa Reddi, Vijay (architecture) John, Lizy (architecture) Patt, Yale (architecture) Swartzlander, Earl (architecture) Tiwari, Mohit (architecture, security) Valvano, Jonathan (embedded medical devices)