ece-c 302 lecture data storage prawat nagvajara stack: last-in first-out (lifo) queue: first-in...
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ECE-C 302 LectureData Storage
Prawat Nagvajara
• Stack: Last-in First-out (LIFO)• Queue: First-in First-out (FIFO)• Random Access Memory
Stack or Last-in First-out (LIFO)Stack Base = 0xFFFF
Location (Address)0xFFE70xFFE80xFFE90xFFFA0xFFFB0xFFFC0xFFFD0xFFFE0xFFFF
Top-of-StackPointer
After 5 pops and a push
Location (Address)0xFFE70xFFE80xFFE90xFFFA0xFFFB0xFFFC0xFFFD0xFFFE0xFFFF
Top-of-StackPointer
And Two More ReadsThe Queue is Empty (Front = Rear)
Location012345670 (end around)
Front PtrRear Ptr
Random Access Memory
• Array of byte or word– Demultiplex when write– Multiplex when read
• SRAM– Instantiation– Used for implementation of embedded FIFO
and stack
• DRAM modulo with asynchronous read and write
Stack and Queue Codespackage s_pack istype integer_array is array (natural range <>) of integer;
type op_type is (push, pop, no_operation);end s_pack;
library ieee;Use ieee.std_logic_1164.all,work.s_pack.all;entity stack isgeneric (d: natural := 256);Port (x: in integer; y: out integer; sel: in op_type; ck: in std_logic);end stack;
-- DESCRIPTION-- ***********-- * A stack is a storage of at most d integers.It is-- last-in first-out data storage similar to a cafeterial-- stack of trays, where data are the trays.-- * The output port y is connected to the top-of-stack (TOS).-- * When a pop operation is selected, the integer stored before-- the top-of-stack becomes the new top-of-stack.-- * When a push operation is selected, the input is stored into-- the top-of-stack and the previous data are pushed down.-- * The transfer of data happens on the clock rising edge.-- * The no_operation select means no datum is transferred.
---- TOS-- ------------------- x ---->| | | ... | |-- y <----| | | ... | |-- ------------------- storage---- Code a behavioral architecture
architecture behav of stack is-- internal signalsignal storage :integer_array(1 to d);
begin
process(ck)beginif ck = '1' then
case sel iswhen push =>storage(1) <= x;for i in 1 to d-1 loop storage(i+1) <= storage(i);end loop;
when pop =>for i in 1 to d-1 loop
storage(i) <= storage(i+1);end loop;when no_operation => null;end case;
end if;end process;y <= storage(1);
end behav;
• Stack (Last-in First-out, LIFO)• Stack design example in Bhasker text p. 273 • Uses the for generate construct to create array of registers • Use component reg8 G1: For k in 1 to N generate
G2: if k = N generate -- top regin <= datain when ctr = ‘1’ else data(k-1); end generate G2; G3: if k>1 and k<N generate regin <= data(k+1) when ctr = ‘1’-- push else data(k-1); -- pop end generate G3; G4: if k=1 generate -- bottom regin <= data(k+1) when ctr = ‘1’ else (others => ‘U’); end generate G4; FF8: Reg8 port map (regin, data(k), ck); End generate G1; Dataout <= data(N);
--First-in first-out queue package FIFO_pack is type integer_array is array (natural range <>) of integer;
type op_type is (push, pop, no_operation); end FIFO_pack; library ieee; Use ieee.std_logic_1164.all,work.FIFO_pack.all; entity FIFO is generic (d: natural := 5); port ( x : in integer; y : out integer; select_operation : in op_type; ck : in std_logic); end FIFO;
DESCRIPTION
* First-In First-Out is a queue - a storage of integers. Operations consist of push, pop and no operation. When pop, the integer that had been first stored is assigned to y and it will be trashed and, an addition storage space is available. When push, an integer at port x is stored.
* EMPTY and FULL conditions: if the queue is full or empty,
an assert statement will be used to indicate the condition when a user try to push or pop, respectively.
architecture behav of FIFO is -- internal signal signal storage : integer_array(1 to d); type state_type is (empty, has_data, full); begin process(ck) variable fp, rp : integer := 1;--front and rear pointers variable q_state : state_type := empty; begin if ck=‘1’ then case select_operation is when no_operation => null;
when push => case q_state is when empty => storage(rp) <= x; if rp = d then rp := 1; else rp := rp+1; end if;--increment w/ end around q_state := has_data; when has_data => storage(rp) <= x; if rp = d then rp := 1; else rp := rp+1;
end if;--increment w/ end around if rp = fp then q_state := full; end if; when full => assert false report "QUEUE FULL" severity ERROR;
end case;
when pop => case q_state is when empty => assert false report "QUEUE EMPTY" severity ERROR;
when has_data => y <= storage(fp); if fp = d then fp := 1; else fp := fp+1; end if;--increment w/ end around if fp = rp then q_state := empty; end if; when full => y <= storage(fp); if fp = d then fp := 1; Else fp := fp+1; end if;--increment w/ end around q_state := has_data; end case; end case;end if;end process; end behav;
RAM
-- Single port Block RAMentity spblockram is
port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(4 downto 0); di : in std_logic_vector(3 downto 0); do : out std_logic_vector(3 downto 0));
end spblockram;architecture syn of spblockram istype ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);signal RAM : ram_type;signal read_a : std_logic_vector(4 downto 0);beginprocess (clk)beginif (clk'event and clk = '1') thenif (we = '1') thenRAM(conv_integer(a)) <= di;end if;read_a <= a;end if;end process;
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