ece 353 introduction to microprocessor systems michael j. schulte week 9

ECE 353Introduction to Microprocessor Systems

Michael J. Schulte

Week 9

TopicsI/O port basicsI/O ports with MSI devicesP compatible devicesAddress decoding for isolated and memory-mapped I/OConditional I/O80C188EB integrated I/O unit82C55A PPI

I/O Port BasicsI/O subsystems allow CPU to interact with the outside worldInput, output, and combined I/O blocksInput ports Byte WordOutput ports Byte WordUnconditional I/O

MSI I/O PortsMedium Scale Integration (MSI) circuits are available to construct portsSimple byte input ports can be constructed from… Octal buffers Octal registersSimple byte output ports can be constructed from octal latches

P Compatible I/O DevicesComplex I/O devices typically require complex interface and control logicP compatible I/O devices have the necessary logic built in to the device itself Interface designed to be reasonably

compatible with many microprocessor buses Need to add decoding/selection logic Examples

Device controllers Used to control complex I/O devices (LCD,

disk drives, etc.) Generic model

I/O Address DecodingI/O address decoding determines the logical location of the I/O device Isolated I/O Memory-mapped I/OInput vs. output ports Same address does not guarantee

same function!Device select pulsesWait statesUsing the CSU with I/O devices

I/O Address Decoding (cont.)PAL/PLA DecodersNonspecific I/O strobes /IOW /IORLinear selectionConventional decoders Device select strobes Cascading

Conditional I/OConditional vs. unconditional transfersHardware examplePolling Overhead Flags / semaphores Wait loops TimeoutsSoftware exercisePossible race condition

80C188EB Integrated I/O Unit

Port 1 FunctionsPort 2 FunctionsBidirectional pin structure SynchronizerProgramming Port Control Register Port Direction Register Port Data Latch Register Port Pin State Register

82C55A Programmable Peripheral Interface (PPI)

LSI device providing 24 bits of I/O Logical organization Block diagramSoftware configurable ports Three modes of operation

Mode 0 Basic Input/Output ports

Mode 1 Strobed Input/Output

Mode 2 Bidirectional data bus

Bit set/reset capability

Real-World ExampleInterface the MAX154 8-bit, 4-channel ADC to the 80C188EB Hardware interface

Use /GCS0 at I/O address 1000h (CSU) Poll conversion status using Port 2.

P2CON / P2DIR / P2LTCH / P2PIN Software interfacing

Write a procedure that does an ADC conversion and then reads the ADC value using mode 1

Input: AL = ADC input channel to use (0-3) Output: ADC value returned in AL

What about mode 0? Timing?

Byte Input Port Example

Byte Output Port Example

74HC540/541

74HC573

74HC574

MAX1200

AD7865

Generic Device Controller(Fig 12.3-2)

control registers

TIMING ANDCONTROL

I/ODEVICE

A(n-1):0

D7:0

/CS/WE/OE

data registers

status registersCPU

CLOCK

address

data

/RD/WR

chip select

HitachiHD44780ULCDController

Port 1 Functions

Port 2 Functions

BidirectionalPort Pin

Port Control Register

Port Direction Register

Port Data Latch Register

Port Pin State Register

Conditional I/O ExerciseWrite a procedure to read data from an input device like the hardware example. Assume that the flag is a READY signal (active high). If the device does not become ready after 1 million polling attempts, return with the carry flag set, otherwise, return with the data in AL and the carry flag cleared.

82C55A Block Diagram

82C55A Modes of Operation

82C55A Mode 1 Input

82C55A Mode 1 Output

Chip-Select Start Reg

Chip-Select Stop Register-Part 1

Chip-Select Stop Register -Part 2

Conditional I/O ExampleD7:0

INPUTDEVICE

Q1

Q2

Q3

Q4

D1

D2

D3

D4

74HC574

CLK <

OC

Q5

Q6

Q7

Q8

D5

D6

D7

D8

A13A14A15

/S2

V CC

A0A1A2

Y0Y1Y2Y3

74HC138

E1E2E3

Y4Y5Y6Y7

/RD

D7Q D

CLK <

PR

CL

74HC7474HC125

vcc

Synchronization