digital electronics part3

Digitaldesign

Combina-torialcircuits

Sequentialcircuits

FSMDdesign

Course contents

• Digital design• Combinatorial circuits: without statusSequential circuits: with status• FSMD design: hardwired processors• Language based HW design: VHDL

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

The flip-flop as building block

• Definitions: Combinatorial circuit: the output is function of the

current value of the inputs Sequential circuit: the output is function of the

current value of the inputs and of the current state (i.e. also function of the sequence of past inputs)

Digitaldesign

Sequentialcircuits

FSMDdesign

The flip-flop as building block

• Definitions Asynchronous sequential circuits: outputs and state

change as soon as an input changes Synchronous sequential circuits: outputs and state

change only when a special input, the clock, gets a certain value

Clock period: duration between two consecutive 10 transitions of the clock

Clock frequency: 1 / (clock period) Duty cycle: (duration that the clock equals 1) /

(clock period) Rising edge: 01 transition of the clock Falling edge: 10 transition of the clock

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity Flip-flop types

• Design of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

SR Latch

Undefined

S R Q(next)

0 0 Q0 1 0

1 1 NA

Digitaldesign

Sequentialcircuits

FSMDdesign

SR Latch

• Note that a Boolean signal now already consists of 5 values: 0: the logical signal “0” 1: the logical signal “1” x: don’t care Z: high impedant U: undefined

• The oscillation is called critical race• The oscillation only happens when the delay

of both gates is exactly equal• When the delays are not equal, the fastest

gates determines the end result: implementation and run-time dependent undefined

Digitaldesign

Sequentialcircuits

FSMDdesign

SR Latch

S R Q(next)

1 1 Q1 0 0

0 0 NA

Set and Reset active low

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Gated SR Latch

C S R Q(next)

0 0 0 Q0 0 1 Q

0 1 0 Q

0 1 1 Q

1 0 0 Q

1 0 1 0

1 1 0 1

1 1 1 NA

C=1: follow inputsC=0: latch outputs

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Gated D Latch

C D Q(next)

C=1: follow inputC=0: latch output

DQ delay when C high: L-to-H delay: 2.4+1.4+1.4=5.2H-to-L delay: 1+2.4+1.4=4.8

CQ delay when D high: L-to-H delay: 2.4+1.4+1.4=5.2when D low: H-to-L delay: 2.4+1.4=3.8

Digitaldesign

Sequentialcircuits

FSMDdesign

Gated D Latch

C D Q(next)

D must not change “immediately before” H-to-L of theclock (during the setup time); reason: clock changesbetween the switching of D and of D’ hence Set andReset switch from H to L at the same time undefined(setup time = H-to-L of invertor)

Digitaldesign

Sequentialcircuits

FSMDdesign

Gated D Latch

C D Q(next)

When D switches at least setup time before the clocktransition, S and R will not switch from H to L at thesame time OK (S is longer high than R, hence Q willcome high following the D input)

Digitaldesign

Sequentialcircuits

FSMDdesign

Gated D Latch

C D Q(next)

Analogously, D may not switch “immediately after” H-to-Lof the clock (during the hold time)

5.2/3.8

SymbolGiven values:5.2=C to QLH

3.8=C to QHL

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block SR Latch Gated SR Latch Gated D Latch Flip-flop sensitivity

Level-sensitive latchMaster-slave flip-flopEdge-triggered flip-flop

Flip-flop types

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Flip-flop types

Digitaldesign

Sequentialcircuits

FSMDdesign

Level sensitive latch

• All previous gated latches are level sensitive Transparent when clock is high Remembering the last value when clock is low

• Level sensitive latches give problems for shift registers for example The input signal may ripple through multiple stages

during one clock-high phase making it very hard to meet setup/hold time

requirements See next slide

Digitaldesign

Sequentialcircuits

FSMDdesign

Level sensitive latch

Two solutions:• Master-slave• Edge-triggered

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Flip-flop types

Digitaldesign

Sequentialcircuits

FSMDdesign

Master-slave flip-flop

Master Slave

Master SlaveX Q1

The master clocks at the falling clock edgeThe slave clocks at the rising edge

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Flip-flop types

Digitaldesign

Sequentialcircuits

FSMDdesign

Edge-triggered flip-flopSet Latch

Reset Latch

Output Latch

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

SR flip-flopJK flip-flopD flip-flopT flip-flopAsynchronous set and reset

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

SR flip-flop

Symbol

Triangle next to clockmeans positiveedge-triggered

Negative edge-triggered

S R Q(next)

0 0 Q0 1 0

1 1 NA

Characteristic table(for design of SR flip-flop)

Q Q(next) S R

0 0 0 x0 1 1 0

1 0 0 1

1 1 x 0

Excitation table(for design with SR flip-flop)Positive level triggered

Negative level triggered

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

JK flip-flop

Symbol

J K Q(next)

0 0 Q0 1 0

1 1 Q’

Characteristic table(for design of JK flip-flop)

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

Excitation table(for design with JK flip-flop)

Circuits that useJK flip-flops are cheaper

than those using SR flip-flops:more don’t cares

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

D flip-flop

Symbol Characteristic table(for design of D flip-flop)

D Q(next)

0 01 1

Excitation table(for design with D flip-flop)

Q Q(next) D

0 0 00 1 1

Designing with D flip-flopis easy

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

T flip-flop

Symbol Characteristic table(for design of T flip-flop)

T Q(next)

0 Q1 Q’

Excitation table(for design with T flip-flop)

Q Q(next) T

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Asynchronous set and reset

Preset

Asynchronous set and reset areuseful to put the flip-flopinitially in a known state

(see lab sessions)

Digitaldesign

Sequentialcircuits

FSMDdesign

• Why are the asynchronous preset and clear connected to both layers of SR-flip-flops? The first layer passes input modifications to the

second layer only at the rising clock edge The second layer reacts immediately, without

waiting for the rising clock edge => needed for asynchronous reaction

If they were only connected to the second layer, the first layer would not know in what state the second layer was put and could give a conflicting command to the second layer at the next rising clock edge, e.g. reset since D=0 and at the same time an asynchronous preset

Digitaldesign

Sequentialcircuits

FSMDdesign

• Why are the asynchronous preset and clear active low? Because ‘wired-or’ of ‘open drain’ circuits is used to

avoid short circuits when there are multiple sources driving them:

Nopreset

preset

Nopreset

preset

Open drain

Implements an AND function (hence ‘wired-or’ ...) with unlimited

number of inputs:The bus is only ‘1’

when all inputs to the bus are equal to ‘1’

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building blockDesign of synchronous sequential circuits• Design of asynchronous sequential circuits• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits

Finite State Machine (FSM) State-based or Moore-type FSM Input-based or Mealy-type FSM Step 1: State diagram Step 2: State minimization Step 3: State encoding Step 4: Choice of the flip-flop type Step 5: Realization of the combinatorial logic Step 6: Timing analysis

• Design of asynchronous sequential circuits• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Finite State Machine

• Design a modulo 4 “Counter”, that counts when the input “CE” (Count Enable) equals 1 and stops counting when the input “CE” equals 0.

• Step 1: translate to a Finite State Machine (FSM):

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

Count=3

Digitaldesign

Sequentialcircuits

FSMDdesign

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

Count=3

Transition to the next state happens at each rising clock edge (a synchronous FSM is clocked!).At each rising clock edge, exactly one transition condition should be true: for each input combination, a transition should be specified in each of the states.

1. We are in state “Count=0”

2. CE input equals 0: we are waiting at the tip of the edge3. CE=1: wait at tip of other edge, but do not count yet!4. Rising clock edge: go to “Count=1”, still with CE=15. CE input becomes 0: wait at tip of other edge6. Rising clock edge: go to “Count=1”, with CE=0

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

Count=3

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

Count=3

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

Count=3

Count=0

CE=0 CE=0

CE=0CE=0

Count=1CE=1

Count=2

Count=3

Digitaldesign

Sequentialcircuits

FSMDdesign

Q1Q0=00

CE=0 CE=0

CE=0CE=0

Q1Q0=01CE=1

Q1Q0=10

Q1Q0=11

• Step 2: Minimise the number of states.It is already the minimum number.

• Step 3: Encode the states:

Digitaldesign

Sequentialcircuits

FSMDdesign

• Step 4: Select the flip-flop type. We select the D type for its simplicity.

• Step 5: Realise the circuit. See next slides:

Digitaldesign

Sequentialcircuits

FSMDdesign

• Translate the FSM in a next-state table:

Q1Q0=00

CE=0 CE=0

CE=0CE=0

Q1Q0=01CE=1

Q1Q0=10

Q1Q0=11

Present state Next state

Q1Q0 Q1nQ0n

CE=0 CE=100 00 0101 01 1010 10 1111 11 00

Digitaldesign

Sequentialcircuits

FSMDdesign

• Determine the excitation functions:Present state Next state

Q1Q0 Q1nQ0n

CE=0 CE=100 00 0101 01 1010 10 1111 11 00

0 0 1 1

0 1 0 1CE

Q1n=D1

Q1Q Q(next) D

0 0 00 1 1

Excitation tablefor D flip-flop

D to be appliedis identical to Qn

0 1 1 0

1 0 0 1CE

Q0n=D0

Digitaldesign

Sequentialcircuits

FSMDdesign

• Implement:

0 0 1 1

0 1 0 1CE

Q1n=D1

0 1 1 0

1 0 0 1CE

Q0n=D0

CE Q1 Q0

Digitaldesign

Sequentialcircuits

FSMDdesign

• Step 6: Timing analysisCE Q1 Q0

CE Q1 Q0

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

State-based or Moore-type FSM

• Design a modulo 4 “Counter”, that counts when the “CE” input equals 1 and stops counting when “CE” equals 0. The output “Y” equals 1 when the count value equals 3.

• Step 1: translate to FSM:

Count=0Y=0

CE=0 CE=0

CE=0CE=0

Count=1Y=0

Count=2Y=0

Count=3Y=1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Be extremely careful about timing issues!! Assume that the Y output is used as a load-enable for a register and as the add/subtract line for an adder/subtractor: when arriving in state 3, Y becomes 1, immediately causing the adder/subtractor to switch to “subtract” mode, but NOT causing the register to load a new value!!! The loading will only occur at the next state transition (i.e. the next clock edge)

CounterCE

Add/Subtract

RegisterLE

A/S’

Clk Clocked

Combinatorial

Digitaldesign

Sequentialcircuits

FSMDdesign

• State-based: the output is indicated for each state the output is only function of the current state, not

of the inputs applied Hence, the output value is indicated in the circle

representing the state

Digitaldesign

Sequentialcircuits

FSMDdesign

Q1Q0=00Y=0

CE=0 CE=0

CE=0CE=0

Q1Q0=01Y=0

Q1Q0=10Y=0

Q1Q0=11Y=1

• Step 2: Minimise the number of states. This is already the minimum number.

Digitaldesign

Sequentialcircuits

FSMDdesign

Digitaldesign

Sequentialcircuits

FSMDdesign

• Translate the FSM in a next-state table:

Q1Q0=00Y=0

CE=0 CE=0

CE=0CE=0

Q1Q0=01Y=0

Q1Q0=10Y=0

Q1Q0=11Y=1

Present state Next state Outputs

Q1Q0 Q1nQ0n YCE=0 CE=1

00 00 01 001 01 10 010 10 11 011 11 00 1

Y isonly

dependenton thecurrentstate,not on

the inputs

Digitaldesign

Sequentialcircuits

FSMDdesign

• Determine the excitation functions:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q Q(next) D

0 0 00 1 1

0 1 1 0

1 0 0 1CE

Q0n=D0

Present state Next state Outputs

Q1Q0 Q1nQ0n Y

CE=0 CE=1

00 00 01 0

01 01 10 010 10 11 0

11 11 00 1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Implement:

0 0 1 1

0 1 0 1CE

Q1n=D1

0 1 1 0

1 0 0 1CE

Q0n=D0

CE Q1 Q0

Digitaldesign

Sequentialcircuits

FSMDdesign

• Step 6: Timing analysisCE Q1 Q0

CE Q1 Q0

Danger for Glitch!

Digitaldesign

Sequentialcircuits

FSMDdesign

• Is a glitch harmful? When the output with the glitch is connected to the

clock of some clocked circuit:

This clocked circuit will unintentionally clock: harmful

Hard to debug: glitch may disappear when probe is connected due to increased capacitance and hence also increased delay

When the output with the glitch is connected to a combinatorial circuit that eventually is the input of a register:

Not harmful, since the register looks at its input only at the clock edge

Dissipates unnecessary power

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Input-based or Mealy-type FSM

• Design a modulo 4 “Counter”, that counts when the “CE” input equals 1 and stops counting when “CE” equals 0. The “Y” output value equals 1 when the count=3 while the input “CE” equals 1.

• Step 1: translate to FSM:

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Digitaldesign

Sequentialcircuits

FSMDdesign

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Transition to the next state happensat each rising clock edge

1. We are in state “Count=2”

2. CE input equals 1: wait at tip of edge with Y=03. Rising clock edge: go to “Count=3”, still with CE=1: Y=14. C input becomes 0: wait at tip of other edge with Y=0;

combinatorial circuit driven by Y reacts, clocked don’t

5. Rising clock edge: Y=0 is clocked into output register

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Count=0

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Count=1CE=1/Y=0

Count=2

CE=1/Y=0

Count=3

CE=1/Y=0

CE=1/Y=1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Be extremely careful about timing issues!! Assume that the Y output is used as a load-enable for a register and as the add/subtract line for an adder/subtractor: when arriving in state 3 with CE=1, Y becomes 1 adder/subtractor switches to “subtract”, but register doesn’t load new value!!! When CE=0, Y becomes 0 adder/subtractor switches to “add”, and LE=0. When the next clock edge comes while CE=0, register will not load.

CounterCE

Add/Subtract

RegisterLE

A/S’

Clk Clocked

Combinatorial

Digitaldesign

Sequentialcircuits

FSMDdesign

• Input-based: the output is specified for each state and each

combination of inputs in that state the output is function of the current state, and of

the applied inputs Hence the output is specified next to each

transition

Digitaldesign

Sequentialcircuits

FSMDdesign

Q1Q0=00

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Q1Q0=01CE=1/Y=0

Q1Q0=10

CE=1/Y=0

Q1Q0=11

CE=1/Y=0

CE=1/Y=1

• Step 2: Minimise the number of states. This is already the minimum number.

Digitaldesign

Sequentialcircuits

FSMDdesign

Digitaldesign

Sequentialcircuits

FSMDdesign

• Translate FSM to next-state table:

Q1Q0=00

CE=0/Y=0 CE=0/Y=0

CE=0/Y=0CE=0/Y=0

Q1Q0=01CE=1/Y=0

Q1Q0=10

CE=1/Y=0

Q1Q0=11

CE=1/Y=0

CE=1/Y=1

Present state Next state/Outputs

Q1Q0 Q1nQ0n/YCE=0 CE=1

00 00/0 01/001 01/0 10/010 10/0 11/011 11/0 00/1

Y doesnot onlydependon thecurrentstate,

but also onthe inputs

Digitaldesign

Sequentialcircuits

FSMDdesign

• Determine the excitation functions:

0 0 1 1

0 1 0 1CE

Q1n=D1

Q Q(next) D

0 0 00 1 1

0 1 1 0

1 0 0 1CE

Q0n=D0

Present state Next state/Outputs

Q1Q0 Q1nQ0n/YCE=0 CE=1

00 00/0 01/001 01/0 10/010 10/0 11/011 11/0 00/1

0 0 0 0

0 0 1 0CE

Digitaldesign

Sequentialcircuits

FSMDdesign

• Implement:

0 0 1 1

0 1 0 1CE

Q1n=D1

0 1 1 0

1 0 0 1CE

Q0n=D0

CE Q1 Q0

0 0 0 0

0 0 1 0CE

Digitaldesign

Sequentialcircuits

FSMDdesign

• Step 6: Timing analysis

CE Q1 Q0

Danger for Glitch!

CE Q1 Q0

Digitaldesign

Sequentialcircuits

FSMDdesign

State-based model

S*=F(S,I)

NextState

Combi-nato-rial

O=H(S)

OutputCombi-nato-rial

Clock Next State S*

CurrentState S

Outputs O

Inputs I

Digitaldesign

Sequentialcircuits

FSMDdesign

Input-based model

S*=F(S,I)

NextState

Combi-nato-rial

O=H(S,I)

OutputCombi-nato-rial

Clock Next State S* CurrentState S

Outputs O

Inputs I

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 1: construction of the FSM

• The first step in the design of synchronous sequential circuits is the construction of the FSM starting from the description in natural language (ambiguous and incomplete)

• Example: Modulo-3 up/down counter Count enable (C):

C=1: countC=0: do not count

Direction (D):D=1: count downD=0: count up

Output (Y): Y=1 when (count equals 2 and we count up) or when (count equals 0 and we count down)

What is the meaning of “We count up”?Do we have to “count” (C=1) and “up” (D=0)or is it sufficient that the direction is “up”

(C=X and D=0)?Ambiguous; I choose for the first

Digitaldesign

Sequentialcircuits

FSMDdesign

• First step: is this a State-based or an Input-based design? It is Input-based, since the output depends on the

state and the input

• Second step: construct the FSM starting from the first state, for each combination of inputs from each state See next slide Note: when an output needs to remain high during

several consecutive states, it should be assigned a ‘high’ value in each of these states!! Each output should be assigned a value in each state!

Digitaldesign

Sequentialcircuits

FSMDdesign

CD=0XY=0

CD=10Y=0

CD=0XY=0

CD=10Y=1

CD=0XY=0

CD=11Y=0

CD=11Y=1

CD=10Y=1

CD=11Y=0

CD=10Y=0

CD=11Y=0

CD=10Y=0

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 2: minimise the number of states

• Goal: less states means less flip-flops• Principal: equivalent behavior of two FSMs• Two FSMs are equivalent when they produce

the same output sequence for the same input sequence

Digitaldesign

Sequentialcircuits

FSMDdesign

• Two states in an FSM may be replaced by 1 state when both states produce the same outputs for the same inputs and when both jump to equivalent next states for the same inputs

• Formally: states sj and sk are equivalent (sjsk) if and only if iI: h(sj,i)=h(sk,i): both states produce the same

output for each combination of inputsand iI: f(sj,i)f(sk,i): the next states are equivalent for

each input combination

Digitaldesign

Sequentialcircuits

FSMDdesign

• In practice: build the next state table out of the state diagram first

NEXT STATE / OUTPUTPRESENTSTATE CD=0X CD=10 CD=11

u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0

Digitaldesign

Sequentialcircuits

FSMDdesign

• Construct the implication table: 1 square per combination of 2 states

u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0u1

u0 u1 u2 d0 d1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Delete all combinations that have different outputs for the same inputs

u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0u1

u0 u1 u2 d0 d1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Indicate for the remaining which next states have to be equivalent to make the current states equivalent

u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0

u0 u1 u2 d0 d1

Minimum numberof states: 3 ie.

{u0,d0}=s0

{u1,d1}=s1

{u2,d2}=s2

Digitaldesign

Sequentialcircuits

FSMDdesign

• Construct the new next state tableNEXT STATE / OUTPUTPRESENT

STATE CD=0X CD=10 CD=11u0 u0/0 u1/0 d2/1u1 u1/0 u2/0 d0/0u2 u2/0 u0/1 d1/0d0 d0/0 u1/0 d2/1d1 d1/0 u2/0 d0/0d2 d2/0 u0/1 d1/0

{u0,d0}=s0

{u1,d1}=s1

{u2,d2}=s2

s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

Digitaldesign

Sequentialcircuits

FSMDdesign

• FYI: draw new state diagramNEXT STATE / OUTPUTPRESENT

STATE CD=0X CD=10 CD=11s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=1

CD=11Y=1

This could have been constructed from the begin-ning, but better 1 state too much than too little

Digitaldesign

Sequentialcircuits

FSMDdesign

• This example did not show how you should manipulate the implication table

• Hence an imaginary example showing all problems:

NEXT STATE / OUTPUTPRESENTSTATE AB=00 AB=01 AB=10

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Construct the implication table: 1 square per combination of 2 states

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s0 s1 s2 s3 s4

Digitaldesign

Sequentialcircuits

FSMDdesign

• Delete all combinations with different outputs for same inputs

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s0 s1 s2 s3 s4

Digitaldesign

Sequentialcircuits

FSMDdesign

• Indicate for the remaining which next states have to be equivalent to make the current states equivalent

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s0 s1 s2 s3 s4

1-41-31-41-3

1-41-3

4-52-4

1-41-3

4-52-4

0-20-21-4

1-41-3

4-52-4

0-20-21-4

1-41-3

4-52-4

0-2, 4-51-2

0-20-21-4

Digitaldesign

Sequentialcircuits

FSMDdesign

1-41-3

4-52-4

0-2, 4-51-2

0-20-21-4

• Delete those states that are equivalent when non-equivalent next states would have been equivalent

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s0 s1 s2 s3 s4

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-20-21-4

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-21-4

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-21-4

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

Digitaldesign

Sequentialcircuits

FSMDdesign

• Delete again as long as states are deleted during an iteration

s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

s0 s1 s2 s3 s4

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

1-4: ?1-3:OK

4-52-4

0-2, 4-51-2

0-2: ?0-2: ?1-4: ?

OK Minimum numberof states: 3 ie.

{s0,s2}=u0

{s1,s3,s4}=u1

{s5}=u2

Digitaldesign

Sequentialcircuits

FSMDdesign

• Construct the new next state tableNEXT STATE / OUTPUTPRESENT

STATE AB=00 AB=01 AB=10s0 s4/1 s2/0 s1/1s1 s2/0 s5/1 s4/1

s2 s1/1 s0/0 s3/1

s3 s2/0 s5/1 s4/1

s4 s0/0 s5/1 s1/1s5 s2/0 s4/1 s2/1

{s0,s2}=u0

{s1,s3,s4}=u1

{s5}=u2

u0 u1/1 u0/0 u1/1u1 u0/0 u2/1 u1/1u2 u0/0 u1/1 u0/1

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding

• n states require at least log2n flip-flops.

• There are n! possible encodings (n choices for the first state, n-1 for the second, etc.)

No. s0 s1 s2 s3 No. s0 s1 s2 s3

1 00 01 10 11 13 10 00 01 112 00 01 11 10 14 10 00 11 013 00 10 01 11 15 10 01 00 11

4 00 10 11 01 16 10 01 11 00

5 00 11 01 10 17 10 11 00 01

6 00 11 10 01 18 10 11 01 007 01 00 10 11 19 11 00 01 10

8 01 00 11 10 20 11 00 10 01

9 01 10 00 11 21 11 01 00 10

10 01 10 11 00 22 11 01 10 0011 01 11 00 10 23 11 10 00 01

12 01 11 10 00 24 11 10 01 00

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding

• Does the chosen encoding matters? Yes. Each choice leads to a different combinatorial

circuit with different cost and delay.

• Often chosen encodings: Straightforward Minimum-bit-change One-hot

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding: Straightforward

• Straightforward encoding uses the binary representation of the state number as code (s0000, s5101, …)

• Straightforward encoding is mostly used when the state number has a physical meaning E.g. a counter whose count value is sent to a

display

• Straightforward encoding is dangerous for glitches and leads to non-minimal area and power consumption: multiple bits have to change at each state transition (multiple bit-changes seldomly happen concurrently; each bit-change requires some logic to implement it; each bit-change consumes power)

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding: Straightforward

s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding:Minimum-bit-change

• For minimum-bit-change encoding we assign the codes such that the total number of bit-changes for all state transitions is minimal

• Minimum-bit-change encoding is mostly used when area and power need to be minimized (CMOS)

Straightforward Minimum-bit-change

Gray codecounter

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding:Minimum-bit-change

All transitions are equally likelyPreferrably only 1 bit difference between each pair of transitions

This can only be realised between two of the three pairs

Possibleencoding:

s0=00s1=10s2=11

s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

00 00/0 10/0 11/1

10 10/0 11/0 00/0

11 11/0 00/1 10/0

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 3: State encoding:One-hot

• Each state has 1 flip-flop, hence no encoding; Q of 1 FF =1, Q of others=0

• Flip-flop cost = O(n) i.o. O(logn), hence only useful for small number of states: controller

• Very easy to realise: short design time (time-to-market, e.g. exam…)

• Very small combinatorial circuits to drive the inputs of the flip-flops: cheap combinatorial part, more expensive flip-flop part An FPGA possesses per half CLB a small

combinatorial circuit and 1 flip-flop: one-hot encoding is ideal for FPGA implementations (except counters: too many states)

Digitaldesign

Sequentialcircuits

FSMDdesign

One-hot encodings0=001s1=010s2=100

s0 s0/0 s1/0 s2/1s1 s1/0 s2/0 s0/0

s2 s2/0 s0/1 s1/0

001 001/0 010/0 100/1

010 010/0 100/0 001/0

100 100/0 001/1 010/0

Digitaldesign

Sequentialcircuits

FSMDdesign

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

DP C C

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Implementation rule for One-hot with D flip-flop: Each arriving transition at a state needs an AND

Digitaldesign

Sequentialcircuits

FSMDdesign

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

CD=10Y=1

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=10Y=0

CD=11Y=0

CD=0XY=0

CD=11Y=1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Implementation rule for One-hot with SR flip-flop: Each arriving transition starting at another state

requires an AND gate at the S input Each departing transition to another state requires

an AND gate at the R input

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 4: Choice of the flip-flop type

• JK flip-flop Most expensive flip-flop Most difficult design Largest number of don’t cares: probably cheapest

(and fastest) combinatorial control logic Used when a different signal sets resp. resets the

flip-flop

• SR flip-flop Cheap flip-flop Difficult design Many don’t cares: probably cheap (and fast) control

logic Used when a different signal sets resp. resets the

flip-flop

Digitaldesign

Sequentialcircuits

FSMDdesign

• D flip-flop Cheap flip-flop Most easy design No don’t cares: probably most expensive (and

slowest) combinatorial control logic Used when the same signal sets resp. resets the

flip-flop, i.e. when the value of a signal has to be remembered temporarily

• T flip-flop Cheap flip-flop Easy design No don’t cares: probably most espensive (and

slowest) combinatorial control logic Used for counters and frequency dividers: fast

toggling

Digitaldesign

Sequentialcircuits

FSMDdesign

• No fixed selection rule exists When we want the cheapest circuit, all variants

have to be tried out When the fastest design time is needed, D flip-flops

are the best choice FPGAs only possess D flip-flops

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 5: Realization of the combinatorial logic: D flip-flop

• Determine the excitation functions

Q Q(next) D

0 0 00 1 1

0 0 x 0

1 0 x 0

0 0 x 1C

0 0 x 1

Q1n=D1

1 0 x 0

0 1 x 0C

0 1 x 0

Q0n=D0

0 0 x 1

1 0 x 0C

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 5: Realization of the combinatorial logic: D flip-flop

0 0 x 0

1 0 x 0

0 0 x 1C

0 0 x 1

Q1n=D1

1 0 x 0

0 1 x 0C

0 1 x 0

Q0n=D0

0 0 x 1

1 0 x 0C

YCost: 35

1.5 CLB

Clr Clr

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 5: Realization of the combinatorial logic: T flip-flop

Q Q(next) T

0 1 11 0 11 1 0

Excitation tablefor T flip-flop

0 0 x 0

1 0 x 0

0 0 x 1C

0 0 x 0

1 0 x 1

0 1 x 1C

0 0 x 0

0 1 x 1

1 1 x 0C

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Digitaldesign

Sequentialcircuits

FSMDdesign

0 0 x 0

0 1 x 1

1 1 x 0C

0 0 x 0

1 0 x 1

0 1 x 1C

Step 5: Realization of the combinatorial logic: T flip-flop

0 0 x 0

1 0 x 0

0 0 x 1C

YCost: 32

Clr Clr

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 5: Realization of the combinatorial logic: SR flip-flop

Excitation tablefor SR flip-flop

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

0 0 x x

1 0 x 0

0 1 x 0

x x x 0

0 x x 1

x 0 x 1

Digitaldesign

Sequentialcircuits

FSMDdesign

Excitation tablefor SR flip-flop

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) S R

0 0 0 x0 1 1 0

1 0 0 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x x 0

0 0 x 1

1 0 x 0

x 0 x x

x 1 x 0

0 1 x x

0 0 x 0

1 0 x 0

0 0 x 1C

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Digitaldesign

Sequentialcircuits

FSMDdesign

0 0 x x

1 0 x 0

0 1 x 0

x x x 0

0 x x 1

x 0 x 1

Digitaldesign

Sequentialcircuits

FSMDdesign

0 x x 0

0 0 x 1

1 0 x 0

x 0 x x

x 1 x 0

0 1 x x

Digitaldesign

Sequentialcircuits

FSMDdesign

0 x x 0

0 0 x 1

1 0 x 0

x 0 x x

x 1 x 0

0 1 x x

0 0 x 0

1 0 x 0

0 0 x 1C

Y Cost: 32

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 5: Realization of the combinatorial logic: JK flip-flop

Excitation tablefor JK flip-flop

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 0 x x

1 0 x x

0 1 x x

x x x 0

x x x 1

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

Digitaldesign

Sequentialcircuits

FSMDdesign

Excitation tablefor JK flip-flop

00 00/0 01/0 10/1

01 01/0 10/0 00/0

10 10/0 00/1 01/0

Q Q(next) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 x x 0

0 x x 1

1 x x 0

x 0 x x

x 1 x x

00 00/0 01/0 10/101 01/0 10/0 00/010 10/0 00/1 01/0

0 0 x 0

1 0 x 0

0 0 x 1C

Digitaldesign

Sequentialcircuits

FSMDdesign

0 0 x x

1 0 x x

0 1 x x

x x x 0

x x x 1

Digitaldesign

Sequentialcircuits

FSMDdesign

0 x x 0

0 x x 1

1 x x 0

x 0 x x

x 1 x x

0 0 x 0

1 0 x 0

0 0 x 1C

Y Cost: 26

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 6: Timing analysis

• Determine maximum clock frequency Max. clock frequency = 1/(delay of critical path) Critical path is the path with the longest

combinatorial delay between two clock edges Example:

Clr ClrQ1

Clr Clr

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 6: Timing analysis• Delay of critical path (assume zero

connection delay): clockQ0 + invertor + 4-input AND + 3-input OR +

setup Dclock = 5.2 + 1.0 + (2.2+1.0) + (1.8+1.0) + 1.0 = 13.2

ns (assuming that our relative times can be considered to be nanoseconds)

fmax = 76 MHz (same assumption)

Clr Clr

Digitaldesign

Sequentialcircuits

FSMDdesign

Step 6: Timing analysis

• After designing the combinatorial circuits for next state and output, all traditional design steps follow: Technology mapping Placement and routing Timing simulation

• Timing simulation is even more important for sequential circuits than for combinatorial circuits Determine the maximum clock frequency to check

whether setup and hold times are satisfied Avoid, if necessary because of connected circuits,

glitches when a state transition involves multiple bit-flips

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuitsDesign of asynchronous sequential circuits• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuits

Definitions and Fundamental Mode Restriction Design

• Basic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Asynchronous Sequential Circuits

• Definitions: Sequential circuit: the output is function of the

current value of the inputs and of the current state (i.e. also function of the sequence of past inputs)

Asynchronous sequential circuits: outputs and state change as soon as an input changes

• Fundamental mode restriction: only one input may change at a time; the next input

change may only occur when all effects to the previous input change died out

• Goal: design of small asynchronous circuits, e.g. interfaces between two synchronous islands with not-correlated clocks or clocks with unpredictable clock skew

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Example circuit: requirements

• Design a circuit with two inputs (I and E) and one output Q. If E is high, a rising edge on I causes Q to go high. Q stays high until E goes low. While E is low, Q is low.

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State transition diagram

Primitive flow table

Minimized flow table

State assignment

Elimination of critical races

Hazard free combinatorial design

Avoidance of input skew

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

State table

• List all states: each possible combination of inputs and outputs is a state

Q I E State

0 0 0 a0 0 1 b0 1 0 c0 1 1 d1 0 0 impossible1 0 1 e1 1 0 impossible

1 1 1 f

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

Q I E State

1 1 1 fa/0

10 00 01

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

We opted for aMoore or state

based design; wecould as well have

chosen a Mealyapproach, with

output pertransition

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

Q I E State

1 1 1 f

SIE00 01 11 10 Q

a a x 0bcdef

SIE00 01 11 10 Q

a a x 0b b x 0cdef

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0def

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0d x d 0ef

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0d x d 0e e x 1f

SIE00 01 11 10 Q

a a x 0b b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x 0b b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x d 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x d c 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e f x 1f x f 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e f x 1f x f c 1

SIE00 01 11 10 Q

a a b x c 0b a b f x 0c a x d c 0d x b d c 0e a e f x 1f x e f c 1

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

• Rule: merge compatible states: states with same next states and outputs or don’t cares

• ‘Compatibility’ is not associative!(a compatible b) AND (a compatible c) does NOT induce (b compatible c)

• Note that minimizing the number of states of synchronous circuits requires equivalence instead of compatibility. States with same outputs and equivalent next

states ‘Equivalence’ is associative!

Digitaldesign

Sequentialcircuits

FSMDdesign

SIE00 01 11 10 Q

Are a and b compatible?SIE00 01 11 10 Q

SIE00 01 11 10 Q

f c 0c x d c 0d x d c 0e e f x 1f x e f c 1

YES, hence merge them

Digitaldesign

Sequentialcircuits

FSMDdesign

Are c and d compatible?S

IE00 01 11 10 Q

YES, hence merge themS

IE00 01 11 10 Q

SIE00 01 11 10 Q

f 0 0e e f x 1f x e f 1

Digitaldesign

Sequentialcircuits

FSMDdesign

Are e and f compatible?

YES, hence merge them

SIE00 01 11 10 Q

f 0 0e e f x 1f x e f 1

SIE00 01 11 10 Q

f 0 0e e f x 1f x e f 1

SIE00 01 11 10 Q

This minimized flow tableis called the

Transition Table

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

State assignment

SIE00 01 11 10 Q

Assume we make followingstraightforward

state assignment:: 00: 01: 11

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Digitaldesign

Sequentialcircuits

FSMDdesign

State assignment

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

0 0 0 x

0 0 1 xE

1 1 1 x

1 1 1 xI

0 0 0 x

0 0 1 xE

1 0 1 x

0 0 0 xI 0 0

Digitaldesign

Sequentialcircuits

FSMDdesign

State assignment

0 0 0 x

0 0 1 xE

1 1 1 x

1 1 1 xI

0 0 0 x

0 0 1 xE

1 0 1 x

0 0 0 xI 0 0

I E S1 S0

Digitaldesign

Sequentialcircuits

FSMDdesign

State assignment

I E S1 S0

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Let’s animate behav from state S=00 with inputs IE=01->11Step 1: Stable state S=00 with inputs IE=01Step 2: Inputs change to IE=11

I E S1 S0

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

I E S1 S0

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Step 3: after 2-input gate delay, OR-gate switches,making S0=1No Step 4: we are stuck in stable state S=01 becauseboth state bits did not change at the same timeThe fact that 2 or more state variables have to change,when 1 input-bit changes is called a RACE CONDITIONWhen this leads to the wrong final state,it’s called a CRITICAL RACE

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

• Solution: make the state assignment such that never 2 or more state variables need to change following a single input change

SIE00 01 11 10 Q

No encoding can be found satisfying the above rule!

Digitaldesign

Sequentialcircuits

FSMDdesign

• Do the state assignment as good as you can. Use additional states to solve the problems that remain

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

Highlight remaining problems

Route these transitions via an additional state, whichdiffers in only one state variable

SIE00 01 11 10 Q

00 00 00 11 01 001 00 00 01 01 011 00 11 11 01 1

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 x 11 x x

Don’t care because bothnew transitions require

an output change: itis not important whetherthis already happens inthe intermediate state

Digitaldesign

Sequentialcircuits

FSMDdesign

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 x 11 x x

0 0 0 0

0 0 1 xE

0 1 1 1

1 1 1 xI

0 0 1 0

0 0 1 xE

1 0 1 1

0 0 0 xI 0 0

Digitaldesign

Sequentialcircuits

FSMDdesign

0 0 0 0

0 0 1 xE

0 1 1 1

1 1 1 xI

0 0 1 0

0 0 1 xE

1 0 1 1

0 0 0 xI 0 0

I E S1 S0

Digitaldesign

Sequentialcircuits

FSMDdesign

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 x 11 x x

What happens at power-up?

The circuit could as well start in state S=10 with aninput of IE=01

It then depends on the actual values of the don’t careswhat is going to happen; it could even remain stablein that state...

It would hence be wise to remove the don’t cares andreplace them with an evolution to a stable state withthe same inputs

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 00 11 01 x

Race, but not critical

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

• The combinatorial circuits of an asynchronous design should be designed in a hazard free way Static hazard: a status variable that is supposed not

to change, briefly changes; this could lead to a wrong final state

Dynamic hazard: a status variable that is supposed to change just once, changes three times; this could lead to a wrong final state

• Synchronous designs do not need to be hazard free, since state variables are only taken into account on a clock edge

• Our design was hazard free, and hence should not be changed

Digitaldesign

Sequentialcircuits

FSMDdesign

Design flow

State table

State assignment

Digitaldesign

Sequentialcircuits

FSMDdesign

• Assume that input I is skewed on the bottom AND gate with respect to the other inputs

I E S1 S0

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 11 11 01 1

Start in state S=01 with IE=11

I becomes 0: S should go to 00

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 11 11 01 1

I E S1 S0

SIE00 01 11 10 Q

00 00 00 10 01 001 00 00 01 01 011 10 11 11 01 110 00 11 11 01 1

I E S1 S0

Now the delayed version of Igoes to zero

State however does not changeanymore and ends in theincorrect S=11

State variables may change only after all inputchanges are applied to all gates!

I E S1 S0

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

• The flip-flop as building block• Design of synchronous sequential circuits• Design of asynchronous sequential circuitsBasic RTL building blocks

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Registers Shift registers Counters

Synchronous countersAsynchronous counters

Register files LIFO queue (push down stack) FIFO queue

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Registers

• Register

D Q D Q D Q D Q

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

Symbol

Digitaldesign

Sequentialcircuits

FSMDdesign

Registers

• Asynchronously presettable and clearable Register

D Q D Q D Q D Q

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Preset

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

SymbolPreset

Digitaldesign

Sequentialcircuits

FSMDdesign

D Q D Q D Q D Q

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Registers

• Loadable register (without gated clock)

• Loads only when “Load=1”• High power dissipation: multiple gates switch whenever the clock changes• No clock skew problems since each flip-flop is clocked by the master clock

Digitaldesign

Sequentialcircuits

FSMDdesign

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

SymbolLoad

Registers

• Loadable register (without gated clock)

Digitaldesign

Sequentialcircuits

FSMDdesign

D Q D Q D Q D Q

I3 I2 I1 I0

Q3 Q2 Q1 Q0

Registers

• Loadable register (with gated clock)

• Clocks only when “CE=1”• Low power dissipation: gates only switch when a newvalue is loaded• Gated clocks (derived clocks) are sensitive to clockskew

Digitaldesign

Sequentialcircuits

FSMDdesign

Registers

• Loadable register (with gated clock)

Register

I3 I2 I1 I0

Q3Q2 Q1 Q0

SymbolCE

Digitaldesign

Sequentialcircuits

FSMDdesign

Registers

• Clock skew problem for gated clocks: Not all clocks of all registers

change concurrently Expected behavior:

New I3..0 applied

At next clock edge:Clk*11, Clk*21 Q*3..0A3..0, A*3..0I3..0

Real behavior:

New I3..0 applied

At next clock edge:Clk*11 A*3..0I3..0, Clk*21Q*3..0A*3..0

Risk for setup violation

Register 1

I3 I2 I1 I0

Register 2

Q3Q2 Q1 Q0

CEA3..0

Digitaldesign

Sequentialcircuits

FSMDdesign

Registers

D0 Q0 D1 Q1

GatedClk

D0 Q0 D1 Q1

Possible setup or hold violation for 2nd flip-flop

D0 Q0 D1 Q1

Digitaldesign

Sequentialcircuits

FSMDdesign

Registers

• What causes clock skew? Gated clocks Different relative routing delay

On PCB and within chip: different wire length

In FPGA: different number of routing switches

• Delay depends on many things: temperature, power supply voltage, fan-out, IC

batch under no circumstance clock skew may cause

problems!!! worst case analysis (e.g. min-delay for data path and max-delay for clock path and vice versa)

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Shift registers

• Serial-in/parallel-out shift register (SIPO)

D Q D Q D Q D Q

Q3 Q2 Q1 Q0

Example of utilization:Receive register (Rx) serial portDelay line for FIR and IIR filters

Digitaldesign

Sequentialcircuits

FSMDdesign

Shift registers

• Serial-in/parallel-out shift register (SIPO)

Shift Register

Q3Q2 Q1 Q0

SymbolSE

Digitaldesign

Sequentialcircuits

FSMDdesign

Shift registers

• Parallel-in/serial-out shift register (PISO)

D Q D Q D Q D Q

Example of utilization: Transmit register (Tx) serial port

I3 I2 I1 I0

Digitaldesign

Sequentialcircuits

FSMDdesign

Shift registers

• Parallel-in/serial-out shift register (PISO)

ShiftRegister

I3 I2 I1 I0

SymbolIL

CESh/Ld’

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Synchronous counters

• Synchronous up-counter

D Q D Q

Clk Q1 Q0

Q2Outputcarry

HAHAHA

Synchronous because all flip-flops are clocked by thesame signal

Digitaldesign

Sequentialcircuits

FSMDdesign

ClkQ1 Q0Q2

Outputcarry

D Q D QD Q

HAHAHA

ClkClear

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

Glitch!

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

D Q D QD Q

HAHAHA

Digitaldesign

Sequentialcircuits

FSMDdesign

• Synchronous up/down-counter

D Q D Q

Clk Q1 Q0

Q2Outputcarry

HASHASHAS

Half adder/subtractor

Digitaldesign

Sequentialcircuits

FSMDdesign

• Design of the Half adder/subtractor

Behavior:When ci=0 then Di=Qi (no counting)When ci=1 this section should toggleC0 has to be 1 when the next section

has to toggle. When should this happen?

Up-count000110110001…

Next section togglesat 10 of this section

Down-count001110010011…

Next section togglesat 01 of this section

Digitaldesign

Sequentialcircuits

FSMDdesign

Up-count000110110001…

Next sectiontoggles at 10of this section

Down-count001110010011…

Up-count000110110001…

Down-count001110010011…

c i Dir Qi Di c i+1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0

Up-count000110110001…

Down-count001110010011…

c i Dir Qi Di c i+1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0

Up-count000110110001…

Down-count001110010011…

c i Dir Qi Di c i+1

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0

Digitaldesign

Sequentialcircuits

FSMDdesign

c i Dir Qi Di c i+1

0 0 0 0 00 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 0 0

0 1 1 0

1 0 0 1ci

0 0 0 0

0 1 0 1ci

Di ci+1

Digitaldesign

Sequentialcircuits

FSMDdesign

• Parallel loadable up/down-counter

Clk Q1

Q2Outputcarry

HASHASHAS

I2 I1 I0

Digitaldesign

Sequentialcircuits

FSMDdesign

• BCD up-counter

Up-counter

I3 I2 I1 I0

Q3Q2 Q1 Q0ELoad

0 0 0 0

Compares with constant:When count equals ‘1001’ (i.e. 9), ‘0000’ is loaded at next clock edge

Digitaldesign

Sequentialcircuits

FSMDdesign

• BCD up/down-counter

Up/down-counter

I3 I2 I1 I0

Q3Q2 Q1 Q0ELoad

0 0 0 01 0 0 1

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Asynchronous counters

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

T Q T Q T Q T Q

Clk Q3 Q2 Q1 Q0

Q’Q’Q’Q’

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

Register files

Register File Cell (RFC)This implementation dissipates much power due to theactive memorization of data, but does not suffer fromclock skew problems.

Combining ‘WE’ with ‘Clk’ into a gated clock, we canreduce the power dissipation

D QDout

Note that in both cases,‘writing’ is clocked, but‘reading’ is not clocked!Needed for critical-path

computation...

Digitaldesign

Sequentialcircuits

FSMDdesign

Register files

RFC RFC RFC RFC

I0I1I2I3

O0O1O2O3

2-to-4writedec

2-to-4readdec

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

LIFO queue - stack

1. Reset45

2. Push 45

3. Push 124. Push 23

5. Pop -> 23

6. Push 10

Digitaldesign

Sequentialcircuits

FSMDdesign

LIFO queue - stack

Enable Push/pop’ Operations

0 0 No change0 1 No change

1 0 Pop

1 1 Push

Using left/right’ shift register

ResetL/R’Enable

and counter for indicationempty/full

Count Empty Full

0000 1 00001 0 0

0010 0 0

0011 0 0

0100 0 0

0101 0 0

0110 0 0

0111 0 0

1000 0 1

Digitaldesign

Sequentialcircuits

FSMDdesign

LIFO queue - stack

ResetL/R’Enable

ResetUp/down’Enable Q3..0

Enable

Reset’

Push/pop’

Digitaldesign

Sequentialcircuits

FSMDdesign

LIFO queue - stack

Alternative implementation: for large stacks

Write Ptr

Read Ptr

3. Push 23

Does not shift!

4. Push 12

2. Push 45

At ‘Push’ both ptrs

count up

5. Pop -> 12

1At ‘Pop’

both ptrs

count down

6. Push 17

1. Reset

empty 0

0=empty

7. Push 52

0=full

Digitaldesign

Sequentialcircuits

FSMDdesign

LIFO queue - stack

RU/D’E

Up/downcounterWrite ptr

SU/D’E

Up/downcounterRead ptr

2-to-1MUX

1Kx8RAM

R/W’

Watch timing of the enable: when RAM is not clockedbe careful not to read/write twice since the counterscount further

Reset’

Push/Pop’

Enable

Full/empty

Datain/out

Note:SET

Digitaldesign

Sequentialcircuits

FSMDdesign

Sequential Circuits

Digitaldesign

Sequentialcircuits

FSMDdesign

FIFO queue

1. Reset45

2. Write 4523

3. Write 23

4. Write 12

5. Read -> 45

6. Write 57

Digitaldesign

Sequentialcircuits

FSMDdesign

FIFO queue

Enable

SetUp/down’Enable Q3..0

Enable

Reset’Read/write’

In7Uit0

0 S2..0

Readpointer

Digitaldesign

Sequentialcircuits

FSMDdesign

FIFO queue

Alternative implementation: for large FIFO’s

Write Ptr

Read Ptr

empty 0

1. Reset2. Write 45

Only write pointer incr.

at write

3. Write 23

Does not shift!

4. Write 12

empty 3

5. Read -> 45

Only read pointer incr.

at read

6. Write 57

empty 0

Wrap-around

7. Write 16

Read and write pointer equal: empty

or full

Digitaldesign

Sequentialcircuits

FSMDdesign

FIFO queue

• Previous implementation indicates empty/full but does not distinguish between both

• Solution: assume queue depth equals 2n

read and write pointer are hence n-bit up-counters select however an (n+1)-bit up-counter:

n-LSB of read and write equal: empty/fullMSB equal: emptyMSB different: fullapply only the n-LSB as address for RAM-

queue• For the stack, we also did not differentiate

between empty and full; how can it be solved there?

Digitaldesign

Sequentialcircuits

FSMDdesign

FIFO queue

11-bit UpcounterWrite ptr

11-bit UpcounterRead ptr

2-to-1MUX

1Kx8RAM

R/W’

Reset’Read/Write’

Enable

Datain/out

FullMSB

10-LSB

digital electronics part3

status sequential circuits

qnext q q q q q

status fsmd design

lauwereins imec

gated d latchd q clock

gated d latchd clock

gated sr latchset q

inputs sequential circuit

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