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1
Jawaharlal Nehru Engineering College
Laboratory Manual
DIGITAL ELECTRONICS
For
Second year Students
20, Feb 2005 – ISO 9000 Tech Document
Author JNEC, Aurangabad
2
FORWARD
It is my great pleasure to present this laboratory manual
for second year engineering students for the subject of DIGITAL
ELECRONICS keeping in view the vast coverage required for circuit
design using VHDL.
As a student, many of you may be wondering with some of the
questions in your mind regarding the subject and exactly what has
been tried is to answer through this manual.
As you may be aware that MGM has already been awarded with
ISO 9000 certification and it is our endure to technically equip our
students taking the advantage of the procedural aspects of ISO 9000
Certification.
Faculty members are also advised that covering these aspects in
initial stage itself, will greatly relived them in future as much of the
load will be taken care by the enthusiasm energies of the students
once they are conceptually clear.
Prof. S.D.Deshmukh.
Principal
3
Vision of JNEC
College seeks to be the engineering college of choice in Maharashtra that can provide the
best learning experience, the most productive learning community, and the most creative
learning environment in Engineering Education and will be recognized as one of the best
Engineering Colleges in India.
Mission of JNEC
To develop innovative engineers with human values, well equipped to solve complex
technical problems, address the needs of modern society and pursue lifelong learning, by
providing them competent, caring and committed faculty.
IT Vision:
IT department is committed to ensure the quality education to students‟ by providing
innovative resources & continuous up-gradation of the department. To achieve “Heights
of Excellence” in the world we strive to organize regular interaction with Industry and
Alumni.
IT Mission:
To impart core technical competency & knowledge in students through curriculum and
certification programs to fulfill the industry requirements which ultimately benefits
society at large.
Program Educational Objectives:
I. Preparation: To prepare students to excel in PG program or to succeed in Industry
/Technical profession through global, rigorous education.
II. Core Competence: To provide students with a solid foundation in mathematical,
scientific and engineering fundamentals required to solve engineering problems and
also to pursue higher studies.
III. Breadth: To train students with good scientific and engineering breadth so as to
comprehend, analyze, design and create novel product and solution for the real life
problems.
IV. Professionalism: To inculcate in students‟ professional and ethical attitude, effective
communication skills, team work skills, multi-disciplinary approach and an ability to
relate engineering issues to broader social context.
V. Learning Environment: To provide students with academic environment aware of
excellence, leadership, written ethical codes and guidelines and lifelong learning
needed for successful professional career.
4
LABORATORY MANUAL CONTENTS
This manual is intended for the second year students of Information
Technology in the subject of DIGITAL ELECTRONICS. This manual typically
contains practical/Lab Sessions related DIGITAL ELECTRONICS covering
VHDL code for various circuit Design.
Although, as per the syllabus, we have made the efforts to cover various
assignments related to various digital circuit design, Students are advised to
thoroughly go through this manual rather than only topics mentioned in the
syllabus as practical aspects are the key to understanding and visualization
the results of various tags of the hypertext markup language.
Good Luck for your Enjoyable Laboratory Sessions!
M.D.PATARE
5
SUBJECT INDEX
1. Study digital ICs and verification of logic gates.
2. Verification of half adder and full adder.
3. Develop VHDL code for 8:1 multiplexer. Simulate and verify its working.
4. Develop VHDL code for 1:8 demultiplexer. Simulate and verify its
working.
5. Develop VHDL code for 3-bit even parity generator and checker.
6. Develop VHDL code for 1-bit digital comparator.
7. Design and develop the VHDL code for D Flip-Flop with
positive- edge triggering. Simulate and verify its working.
8. Design and develop the VHDL code for JK Flip-Flop with positive-edge
triggering. Simulate and verify its working.
9. Develop VHDL code for 4-bit serial-in parallel-out shift register.
10. Develop VHDL code for 4-bit synchronous counter. Simulate and verify
its working.
6
DOs and DON’T DOs in Laboratory:
1. Do not handle any equipment before reading the instructions/Instruction manuals
2. Read carefully the power ratings of the equipment before it is switched on whether
ratings 230 V/50
Hz or 115V/60 Hz. For Indian equipments, the power ratings are normally 230V/50Hz.
If you have equipment with 115/60 Hz ratings, do not insert power plug, as our normal
supply is 230V/50 Hz, which will damage the equipment.
3. Observe type of sockets of equipment power to avoid mechanical damage
4. Do not forcefully place connectors to avoid the damage
5. Strictly observe the instructions given by the teacher/Lab Instructor
Instruction for Laboratory Teachers:
1. Submission related to whatever lab work has been completed should be done during the
next lab session. The immediate arrangements for printouts related to submission on the
day of practical assignments.
2. Students should be taught for taking the printouts under the observation of lab
teacher.
3. The promptness of submission should be encouraged by way of marking and evaluation
patterns that will benefit the sincere students.
7
Lab Assignment No - 1
Aim : Study of digital IC & verification of Logic Gates
Apparatus : Digital IC 7404 (NOT), IC 7432 (OR), IC 7408 (AND), IC 7402(NOR), IC 7400(NAND), IC
7486(EX-OR), Bread board, connecting wires.
1. IC 7408 (Quad 2 input AND gate):
Pin Diagram:
Truth Table:
2. IC 7432 (Quad 2 input OR gate):
Truth Table:
INPUT
A B
OUTPUT
Y= A.B
0 0 0
0 1 0
1 0 0
1 1 1
INPUT
A B
OUTPUT
Y= A+B
0 0 0
0 1 1
1 0 1
1 1 1
8
3. IC 7404 (Hex Inverters):
Truth Table :
4. IC 7400 (Quad 2 input NAND gate):
Truth Table:
Pin Diagram:
Input
A
Output
Y
0 1
1 0
INPUT
A B
OUTPUT
Y= A.B
0 0 1
0 1 1
1 0 1
1 1 0
9
5. IC 7402 (Quad 2 input NOR gate):
Truth Table:
Pin Diagram:
6. IC 7486 (Quad EX-OR gate):
Truth Table:
Pin Diagram:
INPUT
A B
OUTPUT
Y= A+B
0 0 1
0 1 0
1 0 0
1 1 0
INPUT
A B
OUTPUT
Y
0 0 0
0 1 1
1 0 1
1 1 0
10
Procedure:
1. Mount the IC on the bread board
2. Apply +5V supply to the +VCC pin & connect the ground pin to common the power
supply
3. Apply the inputs from the input switches & observe the output on the display LEDs
4. Verify the truth table of the Logic gates.
CONCLUSION: Thus,we have studied digital ICs and verified the logic gates.
11
Lab Assignment No.- 2
Aim: Study & Verification of operation of Half Adder & Full Adder.
Apparatus: Digital IC 7486(EX-OR),7408(AND), 7432(OR),Bread Board, Connecting Wires. Circuit Diagram:
Half Adder: Boolean Equation: Sum = A.B + A.B
Carry = A.B
Circuit Diagram Truth Table:
1.
Full Adder:
Boolean Equation: Sum = A.B.C + A.B.C + A.B.C + A.B.C
Carry = A.B + A.C + B.C
Input Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
12
Circuit Diagram:
Truth Table:
Input Output
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 ,.1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Procedure: 1. Mount the IC's on the bread Board. 2. Make connection as per circuit diagram.
3. Apply +5v supply to the +Vcc pin & Connect the ground pin to common the power supply.
4. Apply the inputs from the input switches & observe the output on the disply LEDs.
5. Verify the truth table of half & full adder.
Conclusion: Thus we have verified the operation of half adder & full adder.
13
Lab Assignment No.- 3
AIM: Develope VHDL code for 8:1 multiplexer. Simulate and verify its working.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
Circuit diagram of 8:1 mux
Truth table
INPUT OUTPUT
S0 S1 S2 Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
D0
D1 D0
11 D2 D0
11 D3 D0
11 D4 D0
11 D5 D0
11 D6 D0
11 D7 D0
11 E D0
11
8:1 mux
SO S1 S2
Y
14
VHDL code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux is
Port ( d0 : in STD_LOGIC;
d1 : in STD_LOGIC;
d2 : in STD_LOGIC;
d3 : in STD_LOGIC;
d4 : in STD_LOGIC;
d5 : in STD_LOGIC;
d6 : in STD_LOGIC;
d7 : in STD_LOGIC;
y : out STD_LOGIC;
sel: in std_logic_vector(2 downto 0) );
end mux;
architecture Behavioral of mux is
begin
process(d0,d1,d2,d3,d4,d5,d6,d7,sel)
begin
case sel is
when "000" => y <= d0;
when "001" => y <= d1;
when "010" => y <= d2;
when "011" => y <= d3;
when "100" => y <= d4;
when "101" => y <= d5;
when "110" => y <= d6;
when others => y <= d7;
end case;
end process;
end Behavioral;
CONCLUSION: Thus we have developed VHDL code for 8:1 multiplexer and
verifified its working
15
Lab Assignment No.- 4
AIM: Develope VHDL code for 1:8 demultiplexer. Simulate and verify its working.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
Circuit Diagram of 1:8 Demux
Truth Table:
INPUT OUTPUT
S0 S1 S2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 Din 0 0 0 0 0 0 0
0 0 1 0 Din 0 0 0 0 0 0
0 1 0 0 0 Din 0 0 0 0 0
0 1 1 0 0 0 Din 0 0 0 0
1 0 0 0 0 0 0 Din 0 0 0
1 0 1 0 0 0 0 0 Din 0 0
1 1 0 0 0 0 0 0 0 Din 0
1 1 1 0 0 0 0 0 0 0 Din
Di
n
Y1 D0 1
1 Y2 D0 1
1 Y3 D0 1
1 Y4 D0
11 Y5 D0 1
1 Y6 D0 1
1 Y7 D0 1
1
E D0 1
1
1:8 Demux
SO S1 S2
Y0 D0
11
16
VHDL CODE:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux is
Port ( din: in std_logic
y0 : out STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC;
y4 : out STD_LOGIC;
y5 : out STD_LOGIC;
y6 : out STD_LOGIC;
y7 : out STD_LOGIC;
sel: in std_logic_vector(2 downto 0) );
end demux;
architecture Behavioral of demux is
begin
process(d0,d1,d2,d3,d4,d5,d6,d7,sel)
begin
case sel is
when "000" => y0 <= din;
when "001" => y1 <= din;
when "010" => y2 <= din;
when "011" => y3 <= din;
when "100" => y4 <= din;
when "101" => y5 <= din;
when "110" => y6 <= din;
when others => y7 <= din;
end case;
end process;
end Behavioral;
CONCLUSION:
Thus, we have developed VHDL code for 1:8 multiplexer.simulated and verifified its
working
17
Lab Assignment No.- 5
Aim: Develop VHDL code for 3-bit even parity generator and checker.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
3-bit even parity generator:
Block Diagram Truth Table
Circuit Diagram:
INPUT OUTPUT
A B C P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
P
3-bit parity
generator
A
B
C
A
B
C
18
VHDL CODE:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity p_generator is
Port ( P: out std logic;
ABC: in std_logic_vector(2 downto 0) );
end demux;
architecture Behavioral of p_generator is
begin
process(ABC,P)
begin
case ABC is
when "000" => P <= „0‟;
when "001" => P<= „1‟;
when "010" => P <= „1‟;
when "011" => P <= „0‟;
when "100" => P <= „1‟;
when "101" => P <= „0‟;
when "110" => P <= „0‟;
when others => P <= „1‟;
end case;
end process;
end Behavior;
19
3-bit even parity checker:
Block Diagram: Truth Table:
Circuit Diagram:
VHDL CODE:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity p_checker is
Port ( PEO: out std logic;
PABC: in std_logic_vector(3 downto 0) );
INPUT OUTPUT
P A B C PEO
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
P A B C 3-bit parity
checker
PEO
P
A
B
C
PEO
20
end demux;
architecture Behavioral of p_checker is
begin
process(ABC,P)
begin
case ABC is
when "0000" => PEO <= „0‟;
when "0001" => PEO<= „1‟;
when "0010" => PEO<= „1‟;
when "0011" => PEO<= „0‟;
when "0100" => PEO <= „1‟;
when "0101" => PEO <= „0‟;
when "0110" => PEO <= „0‟;
when "0111" => PEO <= „1‟;
when "1000" => PEO <= „1‟;
when "1001" => PEO <= „0‟;
when "1010" => PEO <= „0‟;
when "1011" => PEO <= „1‟;
when "1100" => PEO <= „0‟;
when "1101" => PEO <= „1‟;
when "1110" => PEO <= „1‟;
when others => PEO <= „0‟;
end case;
end process;
end Behavioral;
CONCLUSION:
Thus we have verified the operation of 3-bit even parity generator and checker.
21
.
Lab Assignment No.- 6
Aim: Develop VHDL code for 1-bit digital comparator.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
1-bit magnitude Comparator:-
Block Diagram:
Truth Table:
INPUT OUTPUT
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
A B
A>B A=B A<B
1-bit digital comparator
22
VHDL Code:
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity digi_comp is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
agtb : out STD_LOGIC;
aeqb : out STD_LOGIC;
alsb : out STD_LOGIC
);
end digi_comp;
architecture Behavioral of digi_comp is
begin
agtb <= '1' when a>b else '0';
alsb <= '1' when a<b else '0';
aeqb <= '1' when a=b else '0';
end Behavioral;
CONCLUSION:
Thus We have verified the operation of digital comparator.
23
Lab Assignment No.- 7
Aim : Design and develop the VHDL code for D Flip-Flop with positive-edge triggering.
Simulate and verify its working.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
Positive Edge triggered D flip flop:
Block Diagram: Truth Table:
Circuit Diagram:
INPUT OUTPUT
CLK D Qn+1 Qn+1
0 X Qn Qn
1 X Qn Qn
X Qn Qn
0 0 1
1 1 0
CLK
24
VHDL Code:
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fff is
Port ( d : in STD_LOGIC;
resetn : in STD_LOGIC;
set:in STD_LOGIC;
clk: in STD_LOGIC;
q:out STD_LOGIC
);
end fff;
architecture Behavioral of fff is
begin
PROCESS(clk)
BEGIN
if(resetn = '1') then
q <='0';
else if(set='1') then
q <= '1' ;
else if rising_edge(clk) then
q<=d;
else if falling_edge(clk) then
q<='0';
end if;
end if;
end if ;
end if;
END PROCESS ;
end Behavioral;
CONCLUSION:
Thus we have developed VHDL code for positive edge triggered D flip flop and
verified its working.
25
Lab Assignment No.- 8
Aim : Design and develop the VHDL code for JK Flip-Flop with positive-edge triggering.
Simulate and verify its working.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
Positive Edge triggered JK flip flop:
Block Diagram: Circuit diagram using NAND gate:
Truth Table:
26
VHDL Code:-
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jk_ff is
port
(
clk : in std_logic;
J : in std_logic;
K : in std_logic;
Q : out std_logic;
Qbar : out std_logic
);
end jk_ff;
architecture jk_ff_behavioral of jk_ff is
begin
process(clk)
variable Q_temp, Qbar_temp : std_logic;
variable JK_temp : std_logic_vector (1 downto 0) := "00";
begin
if rising_edge(clk) then
JK_temp := (J & K);
case JK_temp is
when "00" => Q_temp := Q_temp;
when "01" => Q_temp := '0';
when "10" => Q_temp := '1';
when "11" => Q_temp := not Q_temp;
when others => Q_temp := Q_temp;
end case;
Q <= Q_temp;
Qbar_temp := not Q_temp;
Qbar <= Qbar_temp;
end if;
end process;
end jk_ff_behavioral;
CONCLUSION:
Thus we have developed VHDL code for positive edge triggered JK
flip flop and verified its working.
27
Lab Assignment No.- 9
Aim : Develop VHDL code for 4-bit serial-in parallel-out shift register.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
4-bit serial-in parallel-out shift register:
VHDL Code:
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shift4 is
Port ( Din : in STD_LOGIC;
Clock,clear: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end shift4;
architecture Behavioral of shift4 is
28
begin
process(clock,clear) begin
if( clear=‟0‟) then Q<=”0000”;
elseif clock EVENT AND clock=‟1‟ then
Q(3)<=din;
Q(2)<=Q(3);
Q(1)<=Q(2);
Q(0)<=Q(1);
End if;
End process;
end Behavioral;
CONCLUSION:
Thus,we have verified the operation of 4-bit serial-in, parallel-out shift register.
29
Lab Assignment No.- 10
Aim : Develop VHDL code for 4-bit synchronous counter.Simulate and verify its working.
TOOL: Xilinx 8.2 ISE Simulator.
THEORY:
4-bit synchronous UP counter
VHDL Code:
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count4 is
Port ( clock : in STD_LOGIC;
enable,clear: in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
Q0 Q3
4-bit synchronous counter
Q1 Q2
Load
(logic1)
Clear P3 P2 P1 P0
clock
Enable
30
end count4;
architecture Behavioral of shift4 is
SIGNAL count:STD_LOGIC_VECTOR(3 downto o);
begin
process(clock,clear) begin
if( clear=‟0‟) then count<=”0000”;
elseif clock‟ EVENT AND clock=‟1‟ then
if(enable=‟1‟) then
count<=count+1;
else
count<=count;
end if;
end process;
Q<=count;
End behavioral;
CONCLUSION:
Thus,We have developed VHDL code for 4-bit synchronous UP counter.
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