dftmax serializer
Post on 11-Nov-2014
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DFTMAX 2010.03Update TrainingUpdate Training
Adaptive Scan with SerializerSe a e
Detailed Overview
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Fewer Pins Are Being Allocated for Test
• Packaging Constraints• Packaging Constraints– Tighter form factors– Higher cost-sensitivityHigher cost-sensitivity
• Core-Based Methodologies– Multiple embedded CODECs
BLK_1 BLK_2
Multiple embedded CODECs– Few chip-level test pins
• Multi-site Testing
BLK_3 BLK_4
u s e es g– Test multiple die simultaneously– Few tester channels
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DFTMAX CompressionLowers Cost of TestLowers Cost of Test
• Widely deployed throughout i d t i d tsemiconductor industry
• Up to 100X or more compression
…Decompressor
compression• Push-button within Design
Compiler®…
p
• Lowest area overhead…
Compressor
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DFTMAX Compression with Few PinsLowers Cost of Pin-Limited TestLowers Cost of Pin Limited Test
• Builds on proven, well established DFTMAX CompressionDFTMAX Compression
• Scales down to 1 scan-in and 1 scan-outUp to 100X compression
…Decompressor
Deserializer
• Up to 100X compression• Maintains same ease-of-use as
DFTMAXS t i ti fl
…
• Supports same insertion flows as DFTMAX
• Same procedures in SPF and same pattern format as DFTMAX …
Compressor
pattern format as DFTMAX• Further reduction in Test Application
Time by “over-clocking”Serializer
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DFTMAX with Serializer
Serializer Clock ControlFSM t
scan_in
• FSM counter– Creates clock enable signal to CGC
and strobe signal to SerializerDriven by some external clock
Deserializer
Decompressor
ser_clk
– Driven by some external clock• CGC
– Produces internally generated clocks for internal scan chains
…
Decompressor
int_clkSerializer
Clock Controller
for internal scan chains• Deserializer
– Loads the scan input data serially and transfers it to Decompressor
Serializer
Compressor
strobe
p• Serializer
– Captures data from Compressor and shifts data serially through scan output
scan_out
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How Serializer Works
scan_in1 serial input *_SCCOMP_DECOMPRESSOR
si4bit Deserializer
ser_clk
strobecom
* lk t*
DecompressorclkA
mbinational
*clockcntrl*
*clkgt*
Serializer ClockCtrl
clockcntrl
scan_out1 serial output
Compressor10
10
10
10
*_SCCOMP_COMPRESSOR
so
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4bit Serializer
How Serializer Works 4 external clock pulses required to load Deserializer
scan_in1 serial input *_SCCOMP_DECOMPRESSOR
si4bit Deserializer
required to load Deserializer
ser_clk
strobecom
* lk t*
clkA
mbinational
*clockcntrl*
*clkgt*
Capture
Serializer ClockCtrl
clockcntrl Capture
scan_out1 serial output
10
10
10
10
*_SCCOMP_COMPRESSOR
soInternal clock pulses every 4 external clock pulses
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4bit Serializer4 external clock pulses
Shift Operation4-Bit Deserializer/Serializer4 Bit Deserializer/Serializer
1. FSM counter i
2. Deserializer starts shifting
3. Deserializer completes shift
5. Tester starts strobing compressor o tp ts for
7. Deserializer l t hift fstarts counting starts shifting
data for first internal shift
completes shift for first internal shift
compressor outputs for first shift
completes shift for last internal shift
9 Counter is 04. First shift data is loaded 6. Tester completes 8. Last shift data is 9. Counter is 0 during captureinto first FFs of internal chains
through decompressorAt the same time, Serializer captures compressor output data
6. Tester completes strobing compressor outputs for first shift
loaded into internal chains through decompressor
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DFTMAX Easy ImplementationLow Effort & Fast Results – ScanLow Effort & Fast Results Scan
set_scan_configuration -chain_count <N>
set dft signal –view existing \
…
set_dft_signal view existing \–type ScanClock -port clk1
create_test_protocol
dft_drc…
preview_dft
insert_dft
write -format verilog -hier -out block1.v
write test protocol -out scan.spf …write_test_protocol out scan.spf
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DFTMAX Easy ImplementationLow Effort & Fast Results – Scan CompressionLow Effort & Fast Results Scan Compression
set_dft_configuration –scan_compression enable
set_scan_configuration -chain_count <N>
set dft signal –view existing \
…Decompressor
set_dft_signal view existing \–type ScanClock -port clk1
create_test_protocol
dft_drc…
preview_dft
insert_dft
write -format verilog -hier -out block1.v
write test protocol -out scan.spf \ …Compressor
write_test_protocol out scan.spf \-test_mode Internal_scan
write_test_protocol -out scancompress.spf \-test_mode ScanCompression_mode
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DFTMAX Easy ImplementationLow Effort & Fast Results – Pin Limited Compression
set scan compression configuration
Low Effort & Fast Results Pin Limited Compression
_ _ p _ g-serialize chip_level
set_dft_configuration –scan_compression enable
set_scan_configuration -chain_count <N>
set dft signal –view existing \
…Decompressor
Deserializer
set_dft_signal view existing \–type ScanClock -port clk1
create_test_protocol
dft_drc…
preview_dft
insert_dft
write -format verilog -hier -out block1.v
write test protocol -out scan.spf \ …Compressor
write_test_protocol out scan.spf \-test_mode Internal_scan
write_test_protocol -out scancompress.spf \-test_mode ScanCompression_mode
Serializer
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Core Level vs. Chip Level
set_scan_compression_configuration–serialize core_level
set_scan_compression_configuration–serialize chip_level
Deserializerser_clk
update_stageupdate_clk
Deserializerser_clk
update_stageupdate_clk
…
Decompressor
scan clk…
Decompressor
scan clk
Compressor
S i listrobe
_
Compressor
S i li
FSMCGC
strobe
_
Serializer
There is no serializer clock controller (FSM, CGC) at the core level
Serializer
During top level integration, clocks and controls will be generated and connected to each core
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User Interface
set_scan_compression_configuration-serialize <chip_level | core_level | none>p_ _
• core_level creates a serialized adaptive scan core for hierarchical flows• chip_level creates a chip level containing serialized adaptive scan cores• none is the default
set_serialize_configuration-test_mode <name>-parallel mode <name>-parallel_mode <name>-inputs <int>-outputs <int>-update_stage <true | false>-exclude clocks <name>-exclude_clocks <name>
• inputs/outputs defines how many ports are used for serializer access• update_stage helps with multi-frequency application• exclude clocks can be used for certain clocks not to be gated by
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• exclude_clocks can be used for certain clocks not to be gated by serializer clock controller
Simple Script Example
• set_scan_compression_configuration defines CODEC• set serialize configuration defines serializer
Deserializer (8bits)
set_scan_compression_configuration \-inputs 8 \ # CODEC inputs
8 \ #
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set_serialize_configuration defines serializer
Decompressor200
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-outputs 8 \ # CODEC outputs-chain_count 200 \ # core chains-serialize chip_level # Enable
update_stage
…200 set_serialize_configuration \
-inputs 1 \ # serial inputs-outputs 1 \ # serial outputspdate stage tr e # pdate stageCompressor
Serializer(8bits)
8-update_stage true # update stage
1FSMCGC
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(8bits)
Deserializer/Serializer Size
• Deserializer/Serializer size is determined byset_scan_compression_configuration –inputs # –outputs #
• Deserializer/Serializer size is equal to # of CODEC inputs and outputsand outputs– If it is 8, an 8 bit Deserializer/Serializer will be implemented
• Deserializer/Serializer segments are determined byset serialize configuration inputs # outputs #set_serialize_configuration –inputs # -outputs #
• Deserializer/Serializer will be divided into some segments– If it is 2, two 4-bit Deserializer/Serializer segments will be created
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g
Clock Edge*_SCCOMP_DECOMPRESSOR
Trailing edge
Trailing edge
ser_clkpll_controller*
lkA
update_stage_clkgtupdate_clk
si
Trailing edge
Decompressor
core
strobecombination
*_clkgt
clkA
int_clk
nal
* SCCOMP COMPRESSOR
Compressor
10
10
10
10
_SCCOMP_COMPRESSOR
so
Leading edge
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Fast External Clock with Serializer4-Bit Deserializer/Serializer4 Bit Deserializer/Serializer
• Internal chain shift clock is generated by l l k di id d b i f S i liexternal clock divided by size of Serializer
• e.g. With 4-bit serialization and external clock d f 20MH th i t ll t dspeed of 20MHz, the internally generated
clock speed is 5MHz• To generate internal clock frequency of 20MHz• To generate internal clock frequency of 20MHz
(to reduce test time), external clock speed should be 80MHz
• Potential timing issue should be considered when a fast external clock is used
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Adaptive Scan with -xtol highwithout Serializerwithout Serializer
*_SCCOMP_DECOMPRESSOR Force PIDecompressor
Scan Clock
Compressor
*_SCCOMP_COMPRESSOR
Strobe
Scan inp ts directl control X tol enabling/disabling and scan path selection
Timing to meet
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Scan inputs directly control X-tol enabling/disabling and scan path selection
Fast External Clock With Serializer4-Bit Deserializer/Serializer Example
*_SCCOMP_DECOMPRESSOR
ser clk
*clockcntrl*
lkA
capture
si
4 Bit Deserializer/Serializer Example
Decompressor
core
ser_clk
strobecombination
*_clkgt
clkA
nal
* SCCOMP COMPRESSOR
Compressor
10
10
10
10
_SCCOMP_COMPRESSOR
so
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Tight Timing
Update Stage (Optional)Solution
• Update stage inserted right after deserializer registers in decompressor block
Solution
in decompressor block• Update stage obtains scan input data from
deserializer registers and holds it for one internal l k l til th fi t i t l hift hclock cycle until the first internal scan shift happens
• It de-couples the combinational path from the external clock timing and provides extra timing g p gmargin
• Results in only one internal clock cycle longer than without update stagewithout update stage
• Test time can be decreased by using faster external clock with update stage
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Update Stage (Optional)Serializer with Update Stage
*_SCCOMP_DECOMPRESSOR
ser_clkupdate_stage_clkgt
“update_clk”
si
Serializer with Update Stagecapture
*clockcntrl*
Decompressor
core
strobecombinat
*_clkgt
clkA
ional
Compressor
10
10
10
10
*_SCCOMP_COMPRESSOR
so
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Relaxed Timing
Serializer Clock Selection
• Deserializer/serializerSynthesized OCCset_dft_clock_controller \
-cell_name pll_controller1 \-design snps clk mux \
register clock is selected as follows
g p _ _ \-pllclocks U_pll/clka \-ateclocks [list <name>] \-cycles_per_clock 2 \-chain_count 1 \test mode OCC MODE
– When OCC controllers are not used
-test_mode OCC_MODE
User-defined OCCset_dft_signal
-type Oscillator
• One of external scan clocks• If pipeline scan data is used,
th i li i t l k i
yp-hookup_pin occ1/clk \-ate_clock [list <name>]-pll_clock U_pll/clka \-ctrl_bits [list \0 occ1/cken0 reg/Q 1 \the pipeline register clock is
used0 occ1/cken0_reg/Q 1 \1 occ1/cken1_reg/Q 1]
set_pipeline_scan_data_configuration \-head pipeline clock <name> \
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head_pipeline_clock <name> \-tail_pipeline_clock <name> \
Serializer Clock Selection
• Selected deserializer/serializer register clock gis shown in preview_dftLoad/Unload Serializer Clock = CLK1
• Update stage register clock is a gated version of the serializer clockversion of the serializer clock
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Predictable Success
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