computing bounds on dynamic power using fast zero-delay logic simulation jins davis alexander

March 16, 2009 SSST'09 1

Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation

Jins Davis AlexanderJins Davis AlexanderVishwani D. AgrawalVishwani D. Agrawal

Department of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849

Objective

• Determine power dissipation in a digital CMOS circuit.

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Components of Power

• Dynamic– Signal transitions

• Logic activity• Glitches

– Short-circuit

• Static– Leakage

Ptotal = Pdyn + Pstat

= Ptran + Psc + Pstat

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Power Per Transition

VVDDDD

GroundGround

CL

R

R

Dynamic Power

= CLVDD2/2 + Psc

Vi

Vo

isc

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Number of Transitions

Problem Statement• Problem - Estimate dynamic power consumed in

a CMOS circuit for:– A set of input vectors– Delays subjected to process variation

• Challenge - Existing method, Monte Carlo simulation, is expensive.

• Find a lower cost solution.

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Bounded (Min-Max) Delay Model

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• EA is the earliest arrival time• LS is the latest stabilization time• IV is the initial signal value• FV is the final signal value

IV FV

LSEA

IV FV

EA LS

[d, D]EAdv LSdv

EAsv=-∞ LSsv=∞

EAsv LSsv

EAdv=-∞ LSdv=∞

Drivingvalue

Sensitizingvalue

Example

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d D

d D

Finding Number of Transitions

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2, 2

1, 3

3 14

5 8 10 12

7 10 12 14

5 17

EA LS

3 14

EA LS

[0,4]

[0,2] 6 17

EA LS

[mintran,maxtran]

where mintran is the minimum number of transitions and maxtran the maximum number of transitions.

Estimating maxtran• Nd: First upper bound is the largest number of transitions

that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV, FV) output values.

• N: Second upper bound is the sum of the input transitions as the output cannot exceed that. Further modify it as

N = N – k

where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs.

• The maximum number of transitions is lower of the two upper bounds:

maxtran = min (Nd, N) March 16, 2009 SSST'09 10

First Upper Bound, Nd Nd = 1 + (LS – EA)/d

└ ┘

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d, D

EA LS

d

Examples of maxtran

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Nd = 1 + (18 – 3)/0 = ∞

N = 4 + 4 = 8

maxtran=min (Nd, N) = 8

Nd = 1 + (23 – 6)/3 = 6

N = 4 + 4 = 8

maxtran=min (Nd, N) = 6

Example: maxtran With Non-Zero k

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EAsv = - ∞

EAdv

LSdv = ∞

LSsv

EAsv = - ∞ LSdv = ∞

EAdv LSsv

EA LS

[n1 = 6]

[n2 = 4]

[n1 + n2 – k = 8 ] ,

where k = 2

[ 6 ]

[ 4 ]

[ 6 + 4 – 2 = 8 ]

Simulation Methodology

• d, D = nominal delay ± Δ%• Three linear-time passes for each input vector:

First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals.

Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and bounded gate delays.

Third pass: determines upper and lower bounds, maxtran and mintran, for all gates from the above information.

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15

Zero-Delay Vs. Event-Driven Simulation

0

1000

2000

3000

4000

5000

6000

7000

8000

9000

357 514 880 1161 1667 2290 2416 3466

Ex

ec

uti

on

Tim

e (

se

cs

)

Number of gates

Event driven simulation

Min-Max Simulation

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Maximum Power• Monte Carlo Simulation vs. Min-Max analysis for circuit C880.

100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors).

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R2 is coefficient of determination, equals 1.0 for ideal fit.

Minimum Power

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R2 is coefficient of determination, equals 1.0 for ideal fit.

Average Power

R2 = 0.9527

0

1

2

3

4

5

6

7

8

9

10

0 2 4 6 8 10

MIN - MAX mean power (mW)

Mo

nte

Car

lo a

vera

ge

po

wer

(m

W)

R2 is coefficient of determination, equals 1.0 for ideal fit.

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C880: Monte Carlo vs. Bounded Delay Analysis

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Monte Carlo Simulation Bounded Delay Analysis

Min Power (mW)

Max Power (mW)

CPU Time (secs)

Min Power (mW)

Max Power (mW)

CPU Time (secs)

1.42 11.59 262.7 1.35 11.89 0.3

0

10000

20000

30000

40000

50000

60000

70000

80000

Power (mW)

Fre

qu

en

cy

1000 Random Vectors, 1000 Sample Circuits

Power Estimation Results• Circuits implemented using TSMC025 2.5V CMOS library , with standard

size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulations were run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM.

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Conclusion• Bounded delay model allows power estimation

method with consideration of uncertainties in delays.

• Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis.

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