cmos circuit design for minimum dynamic power and highest speed tezaswi raja, dept. of ece, rutgers...
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CMOS Circuit Design for CMOS Circuit Design for Minimum Dynamic Power and Minimum Dynamic Power and
Highest SpeedHighest Speed
Tezaswi Raja, Dept. of ECE, Rutgers University
Vishwani D. Agrawal, Dept. of ECE, Auburn University
Michael L. Bushnell, Dept. of ECE, Rutgers University
Research Funded by: A National Science Foundation Grant
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 2
Talk OutlineTalk Outline
MotivationObjectivePrior WorkNew ApproachResultsConclusion and Future Work
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 3
Motivation Motivation Power consumption due to glitches can exceed 30-
40% of total power consumption.
Existing linear programming techniques eliminate
glitches, but may insert delay buffers when overall
circuit delay is constrained.
Delay buffers consume power themselves and thus
reduce power saving – also chip area increases.
Example: c1355, a 619-gate circuit needed 224 buffers
-- 36 % increase in gates – for 42% power saving and
no IO delay increase.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 4
Problem StatementProblem StatementFind a linear program (LP) to determine
gate delays in a CMOS circuit such that:
• All glitches are eliminated
• No delay buffers are inserted in the circuit
• Circuit operates at the highest possible speed permitted by the device technology.
Note: The objective is to minimize switching power. Hence, no attempt is made to reduce short-circuit and leakage power, which is an order of magnitude lower for present CMOS technologies; those components of power may be addressed in the future research.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 5
CMOS Power DissipationCMOS Power DissipationShort circuit power Leakage power (IDDQ)Dynamic power
• Essential transitions• Glitches• Each transition dissipates CV2/2
Short circuit and leakage power components are at least an order of magnitude lower than the dynamic power in present day technologies.
V
C
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 6
What Are Glitches?What Are Glitches?
Glitches occur due to differential (unbalanced) path delays.
Glitches are transients that are unnecessary for the correct functioning of the circuit.
Glitches waste power in CMOS circuits.
Delay =12
2
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 7
Glitch SuppressionGlitch Suppression Differential Path Delay
Path P1
Path P2
Differential Delay = |delay (P1) – delay (P2)|; it is the width of the maximum potential glitch at the gate output.
For complete glitch suppression: for each gate, inertial delay > differential delay
To satisfy this condition, previous low-power design methods insert delay buffers in the circuit.
Power will be further reduced if glitch suppression could be achieved without buffers.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 8
Example: Why Use Buffers?Example: Why Use Buffers?
Delay unit is the smallest delay possible for a gate in a given technology.
Critical Path is the longest delay path in the circuit and determines the speed of the circuit.
1
1
1
Critical path delay = 3
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 9
For glitch free operation of first gate: Differential delay at inputs inertial delay OK
1
1
1
Example (cont.)Example (cont.)0
0
time
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 10
1
1
1
Example (cont.)Example (cont.)
For glitch free operation of second gate: Differential delay at inputs inertial delay OK
1
0
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 11
1
1
1
Example (cont.)Example (cont.)
For glitch free operation of third gate: Differential delay at inputs inertial delay Not true for gate 3
2
0
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 12
1
1
1
Example (cont.)Example (cont.)
For glitch free operation with no IO delay increase: Must add a delay buffer.
Buffer is necessary for conventional gate design – only gate output delay is controllable.
2
11
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 13
1
1
Controllable Input Delay Gates Controllable Input Delay Gates
Assume gate input delays to be controllable Glitches can be suppressed without buffers
2
0
1
2
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 14
Delay Model for a New GateDelay Model for a New Gate
Separate the output (inertial) and input delay components.
d3 - output delay of the gate. d3,1 - input delay of the gate along path from 1 to 3. Gate design is feasible and is under development... Technology constraint: input delay difference has an
upper bound, which we define as Gate Input Differential Delay Upper Bound ( ub ).
d3,1 + d33
1
2 d3,2 + d3
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 15
Gate Input Differential Delay Upper Gate Input Differential Delay Upper Bound (Bound (uubb))
It is a measure of the maximum difference in delay of any two IO paths through the gate, that can be designed in a given CMOS technology.
Arbitrary input delays cannot be realized in practice due to the technology limitation at the transistor and layout levels.
The bound ub is the limit of flexibility allowed by the technology to the designer at the transistor and layout levels.
The following feasibility condition must be imposed while determining delays for glitch suppression:
0 0 d di, j i, j uubb
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 16
A New Linear ProgramA New Linear Program Contains following components
• Variables Gate inertial delay variables (di) Input delay variables (di,j) Timing window variables
• Constraints Gate delay constraints Gate input delay upper bound constraints Differential delay constraints Maximum delay constraints
• Objective function Let us consider a simple example combinational
circuit.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 17
6
New LP ExampleNew LP Example51
72
3
4 Gate inertial delay variables d5 ..d7
Gate input delay variables di, j for every path through gate i from input j
Corresponding window variables t5 ..t7 and T5 ..T7.
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 18
6
New LP Example (cont.)New LP Example (cont.)51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Inertial delay constraint for gate 5: dd55 1 1 Input delay constraints for gate 5:
• 0 0 d d5,1 5,1 u ubb
• 0 0 d d5,2 5,2 u ubb
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 19
6
New LP Example (cont.)New LP Example (cont.)51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Differential delay constraints for gate 5:
T5 > T5,1 + d5; t5 < t5,1 + d5; d5 > T5 – t5;
T5 > T5,2 + d5; t5 < t5,2 + d5;
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 20
6
New LP Example (cont.)New LP Example (cont.)51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Differential delay constraints for gate 5:
T5,1 > T5 + d5,1; T5,2 > T5 + d5,2;
t5,1 < t5 + d5,1; t5,2 < t5 + d5,2;
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 21
6
New LP Example (cont.)New LP Example (cont.)51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
IO delay constraint for each PO in the circuit:
T7 maxdelay;maxdelay is the parameter which gives the delay of the critical path.This determines the speed of operation of the circuit.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 22
6
New LP Example (cont.)New LP Example (cont.)51
72
3
4
d5,1 + d5
d7,4 + d7
d5,2 + d5
d6,2 + d6
d6,3 + d6
d7,5 + d7
d7,6 + d7
Objective Function: minimize maxdelay; This gives the fastest and lowest dynamic power consuming
circuit, given the feasibility condition for the technology.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 23
Solution CurvesSolution Curves
ub=0ub=5ub=10ub=15ub= ∞
Fastest Possible Design
Minimum Dynamic
power
Maxdelay
Power
Power consumed by buffers
Previous solutions with buffers
New solutions
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 24
ResultsResults: : Procedure OutlineProcedure Outline
C++ Program
AMPL
Power Estimator
Combinational circuit netlist
Results
Constraint-set
Optimized delays
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 25
Results on Feasibility Upper Bound (uResults on Feasibility Upper Bound (ubb))
Maxdelay is normalized to the fastest possible circuit design. Each curve is a different benchmark circuit. As we increase ub, the circuit becomes faster.
Flexibility required for fastest operation of circuit is proportional to the size of the circuit.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 26
Results: Low-Power DesignResults: Low-Power DesignCircuit Unoptimized
power
Optimized
power
No. of vectors
maxdelay Norm. delay
ub
c432 1.0 0.52 56 71 4.17 5
1.0 0.49 56 27 1.58 10
1.0 0.48 56 17 1.00 15
c499 1.0 0.70 54 34 2.26 0
1.0 0.75 54 15 1.00 5
c880 1.0 0.48 78 45 1.50 10
1.0 0.47 78 30 1.00 15
c1355 1.0 0.47 87 71 2.95 10
1.0 0.46 87 46 1.91 15
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 27
Comparison with Conventional Gate Comparison with Conventional Gate
Design (Design (uubb=0) (Raja =0) (Raja et alet al., ., VLSI DesVLSI Des. `03). `03)
Conventional gates Variable input delay gates
Circuit Power maxdelay Buffers Power maxdelay ub
c432 0.72 1.0 95 0.48 1.0 15
0.62 2.0 66 0.49 1.58 10
c499 0.91 1.4 48 0.75 1.00 15
0.70 2.2 0 0.70 2.26 10
c880 0.68 1.0 62 0.47 1.00 15
0.68 2.0 34 0.48 1.50 10
c1355 0.58 1.0 224 0.46 1.00 15
0.57 2.0 192 0.47 2.08 10
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 28
ConclusionConclusion Main idea: Minimum dynamic power circuits can be
designed if gates with variable input delays are used.
The new design suppresses all glitches without any
delay buffers.
Speed of the new design depends on the gate input
delay variability allowed by the technology.
A linear program solution demonstrates the idea.
Results show average power savings up to 52%.
Future work: Variable input delay gate design.
Jan 9, 2004 Int'l Conf. on VLSI Design, 2004 29
Thank youThank you
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