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Oct 22, 2006 FDIP-06 1
Characterizing and Managing Variability in Microprocessor Chips
Manjul Bhushan
IBM, Systems & Technology Group
Oct 22, 2006 FDIP-06 2
Acknowledgements
• Mark Ketchen
• Anne Gattiker
• IBM Systems & Technology Group Members
References:
1. Manjul Bhushan, Anne Gattiker, Mark B. Ketchen, and K.K. Das
IEEE Transactions on Semiconductor Manufacturing, 19, pp10-18, 2006.
2. Manjul Bhushan, Mark B. Ketchen, Stas Polonsky and Anne Gattiker
Proceedings of 2006 ICMTS
3. Mark B. Ketchen and Manjul Bhushan
IBM Journal of Research and Development, Vol 4/5, 2006
4. Anne Gattker, Manjul Bhushan and Mark B. Ketchen, ITC -2006.
Oct 22, 2006 FDIP-06 3
Outline
• Source of Variability and Impact
• Measuring Variability
- Process Induced
- Design Induced
• Managing Variability
• Summary
Oct 22, 2006 FDIP-06 4
Variability - Challenges
Characterization Goal: Reduce impact of variability on microprocessor performance, power and yield
Characterization
Reduction Accommodation50 100 150 200 250 300
0
20
40
60
dL/L
dVt
Technology Node
65nm 250 nm
∆Vt
∆L/L
Oct 22, 2006 FDIP-06 5
Sources of Variability (CMOS Technology)
• Fundamental Random Variations- Dopant fluctuations induced Vt variations- Line edge roughness
• Systematic CMOS process induced variations- Across chip, across reticle, across wafer,
wafer-to-wafer and lot-to-lot- Across circuit topology & metal wire R & C
• Time dependent variations, short term (10-9 s - 10-3 s)- SOI Floating body induced variations- Power supply transients
• Time dependent variations, long term (108 s)– NBTI, hot-electron, electromigration
Oct 22, 2006 FDIP-06 6
Sources of Variability (Package/ Design)
• Chip integration induced variation- Power supply distribution- Hotspots
• Package/module induced variations
- IR Drops
- Temperature gradients
• Design tool induced variations- Hardware to parasitic and wire models
- Hardware to BSIM model
- BSIM model to piecewise linear model
Oct 22, 2006 FDIP-06 7
Is Variability an Issue?
• Reduced yield forhigh performance parts
• SRAM yield – read/write fails
• Analog circuits – functionality,
out of specifications
IDD
Q
Ckt Delay
Functional
yield
Oct 22, 2006 FDIP-06 8
Characterizing Variability
• Product representative test structures
- on chip placement for ongoing evaluation
- design tools based target parameters
- experimental designs to minimize ambiguity
• Ease of data collection, development and manufacturing
• Techniques for effective data analysis
• Rapid feedback to CMOS process and design teams
Oct 22, 2006 FDIP-06 9
“At Speed” Test Structures
Analog Inputs for Tuning
Set / Reset
Inputs
High Speed
Circuits
Enable / LaunchLow Frequency /
DC Output
Digital Inputs
for DecodersGND VDD’s
Analog Inputs for Tuning
Set / Reset
Inputs
High Speed
Circuits
Enable / LaunchLow Frequency /
DC Output
Digital Inputs
for DecodersGND VDD’s
• Strategic placement
• Ring oscillator and pulse based
• Differential measurements/analysis
• DC I/O’s for ease of measurement
• Circuit delays directly relate to process/device parameters
µP µP
Scribe line
Oct 22, 2006 FDIP-06 10
• Process induced systematic variations- Across chip- Across circuit toplogies / layout Styles
• Random variations in closely spaced identical circuits, arising from variations in Vt, Line width (Lpoly), Tox ..
Test Structures for rapid measurements of product representativeidentical ckt. delays to obtain underlying parametric variations
Variability in Circuit Performance
Oct 22, 2006 FDIP-06 11
Across Chip VariationMultiple Identical Ring Oscillators
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
8
9
10
11
12
10 7 4 1
11 78
12 79 76 3
5 2
Microprocessor Chip
• Placement of identical ring oscillators
on a grid
• > 50 stages/ring to remove impact of
random variations in MOSFET parameters
• Measurement (w & w/o clock) for CMOS
performance variations vs. power supply and temperature variations
• Correlation of ring and chip frequency
by location
Oct 22, 2006 FDIP-06 12
Delay Variation Across Chip
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
8
9
10
11
12
10 7 4 1
11 78
12 79 76 3
5 2
Microprocessor Chip
Fast Slow
• Higher IDDQ for constant Fmax• Fmax variation across wafer
Oct 22, 2006 FDIP-06 13
Across Circuit Type/Process Variability
Expected correlation
Oct 22, 2006 FDIP-06 14
Ring Oscillator Stage Designs Differencing Schemes
NPG
Cg
Cw
Rw
(a) Reference Stage (b) Capacitance Load - C
(c) Wire Load - RC (d) MOSFET Load - R
Oct 22, 2006 FDIP-06 15
Design of a 32 Ring Oscillator Macro
OUTFrequency Divider
and I/O Driver
Decoder
8 RO’s
2.5 mm
Oct 22, 2006 FDIP-06 16
Average Current from RO Delay/Stage
Inverter + N_passgate Stage
Rsw = D/Cs
N
P
Inverter Stage 0 1
Vds/Vdd
0
1
Jd
s/J
on
N
NA
NB
NC
NAND3 Stage
0 1
Vds/Vdd
0
1
Jd
s/J
on
NB
NC
NA
N
NPG
0 1
Vds/Vdd
0
1
Jd
s/J
on
NPG
Oct 22, 2006 FDIP-06 17
“At Speed” Test Structure for Vt Variations
CLOCK RO Divide by m
Decoder
Counter
ENABLE
MUX
F_OUT
Array RO’s
Time
8TT
Frequency Modulated Output
Oct 22, 2006 FDIP-06 18
Extraction of Vt Variations from Circuit Delays
Inverter
NFET
Passgate
RO Stage
Simulated % Change in RO Freq. vs.VddδVt =+/- 40 mV, δ Lp =+/-12%
Lp
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
Vdd (V)
0
20
40
60
80
100
120
Ch
an
ge
in
Fre
qu
en
cy
(%
)
Vt
0.6 0.7 0.8 0.9 1.0
Vdd (V)
20
40
60
Sig
ma V
t (m
V)
Array1
Array2
Array3
Oct 22, 2006 FDIP-06 19
Temporal Variability – SOI History Effect
StgStgStgStg StgOUTIN
Primary Delay Chain
Wi Wo
1SW Delay > 2SW Delay
9
12
12
99
1212
12
9
12
Wafer
Oct 22, 2006 FDIP-06 20
Variability introduced by Chip Timing Tools
• Simulated circuit delays vary with parasitic models
• Model assumptions to reduce simulation time add toinaccuracies in timing
0 5 10 15 20
Ckt #
0
5
10
% C
han
ge in
Dela
y
Example: Circuit delay w & w/o node-to-node coupling capacitance
Bottom switching
NANDs/NORs
Miller cap. Narrow gate
Top switching
NANDs/NOR
Oct 22, 2006 FDIP-06 21
Multiple Vt MOSFETs – Inverter FO3
• IDDQ vs. Delay for two different Vt’s• Shifts in relative Vt centering in the hardware may
merge the distributions
0.8V
Vdd=0.8V Vdd =1.0V
Vt1
Vt2
Vt1
Vt2
Ckt Delay Ckt Delay
IDD
Q
Oct 22, 2006 FDIP-06 22
Multiple Vt’s, Critical Path Example
Vt1
Vt2Vt1/Vt2
(Vt1+30mV)/Vt2
Path composition
All Gates Vt1
All Gates Vt2
Mixed Gates Vt1/Vt2
Mixed Gates (Vt1+30mV)/Vt2
IDD
Q
Path Delay
Leakage Power (IDDQ) /Performance Trade-off varies
with mixed Vt gates and Vt centering in the Hardware
Oct 22, 2006 FDIP-06 23
Summary
• Characterization of variability on an on-going basis is key to its minimization and accommodation in design
• “At Speed” test structures for variability
characterization aid in technology development and manufacturing
• Judicious composition of device menu and
restrictive designs reduce the impact of variability
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