chapter 7 function-architecture codesign paradigm

Chapter 7 Function-Architecture Codesign Paradigm

Function Architecture Co-design Methodology

System Level design methodology

Top-down (synthesis)

Bottom-up (constraint-driven)

Synthesis Verification

Function Architecture

Mapping

Trade-off

Co-design Process Methodology

System Level Design Vision

Functioncasts a shadow

Abstraction

Refinement

Architecturesheds light

Constrained Optimization Constrained Optimization

and Co-designand Co-design

Main Concepts

Decomposition

Abstraction and successive refinement

Target architectural exploration and estimation

Decomposition

Top-down flow Find an optimal match between the application

function and architectural application constraints (size, power, performance).

Use separation of concerns approach to decompose a function into architectural units.

Abstraction & Successive Refinement

Function/Architecture formal trade-off is applied for mapping function onto architecture

Co-design and trade-off evaluation from the highest level down to the lower levels

Successive refinement to add details to the earlier abstraction level

Target Architectural Exploration and Estimation

Synthesized target architecture is analyzed and estimated

Architecture constraints are derived An adequate model of target architecture is built

Architectural Exploration in POLIS

Main Steps in Co-design and Synthesis

Function architecture co-design and trade-off– Fully synthesize the architecture?– Co-simulation in trade-off evaluation

• Functional debugging • Constraint satisfaction and missed deadlines• Processor utilization and task scheduling charts• Cost of implementation

Mapping function on the architecture– Architecture organization can be a pre-designed collection of components

with various degrees of flexibilities– Matching the optimal function to the best architecture

Function/ Architecture Co-design vs. HW/SW Co-design

Design problem over-simplified Must use Fun./Arch. Optimization & Co-design to

match the optimal Function to the best Architecture1. Fun./Arch. Co-design and Trade-off

2. Mapping Function Onto Architecture

Reactive System Co-synthesis(1)

Control-dominated Design

EFSM Representati

CDFG Representati

Decompose Map

EFSM: Extended Finite State Machines

CDFG: Control Data Flow directed acyclic Graph

Reactive System Co-synthesis(2)

CDFG is suitable for describing EFSM reactive behavior but

Some of the control flow is hiddenData cannot be propagated

S1a:= a + 1

S0a:= 5

Mapping

a := 5a := 5

state := S1

Case (state)Case (state)

BEGINBEGIN

ENDEND

a := a + 1

state := S2

emit(a)emit(a)

EFSMRepresentation

a:= a + 1a:= 6

Optimized EFSMRepresentation

Data Flow Optimization

Optimization and Co-design Approach

Architecture-independent phase

– Task function is considered solely and control data flow analysis is performed

– Removing redundant information and computations

Architecture-dependent phase

– Rely on architectural information to perform additional guided optimizations tuned to the target platform

Graphical EFSM Esterel

ReactiveVHDL Specification

FFGFFG

AUXModeling

Function Architecture

AFFGAFFG

SHIFT(CFSM Network)

FunctionalOptimization

Macro-levelOptimization

Micro-levelOptimization

ResourcePool

BehavioralOptimization

Cost-guidedOptimization

HW/SWRTOS/InterfaceCo-synthesis

Decomposition

Constraints

SW Partition HW Partition

Processor

HW4HW3

Concrete Co-design Flow

Design

Representation

Function/Architecture Co-Design

Function/ArchitectureOptimization and Co-design

Design

Application

Decomposition

controlcontrol

datadata

i/oi/o

ASICsASICsprocessorsprocessors

fsmfsmfsmfsmdata f.data f.data f.data f.II OO

Processor

HW4HW3

RTOS Hardware/Software Co-synthesis

Mapping

Abstract Co-design Flow

Design

IDRIDR

Architecture Independent

Architecture Dependent Constraints

Unifying Intermediate Design Representation for Co-design

Intermediate Design Representation

Functional Decomposition

Architectural Space

Application Space

Application Instances

Platform Instance

System Platform

Platform Design Space Exploration

Platform Specification

Platform-Based Design

Source: ASV

Models and System

Models of computation

– Petri-net model (graphical language for system design)

– FSM (Finite-State Machine) models

– Hierarchical Concurrent FSM models

POLIS system

– CFSM (Co-design FSM)

– EFSM (Extended FSM): support for data handling and asynchronous communication

Includes

– Finite state machine

– Data computation

– Locally synchronous behavior

– Globally asynchronous behavior

Semantics: GALS (Globally Asynchronous and Locally Synchronous communication model)

C=>FB=>C

F^(G==1)

(A==0)=>B

C=>ACFSM1

CFSM Network MOC

MOC: Model of Computation

Communication between CFSMs by means of events

System Specification Language

“ Esterel”

– as “front-end” for functional specification

– Synchronous programming language for specifying reactive real-time systems

Reactive VHDL

Graphical EFSM

Intermediate Design Representation (IDR)

Most current optimization and synthesis are performed at the low abstraction level of a DAG (Direct Acyclic Graph).

Function Flow Graph (FFG) is an IDR having the notion of I/O semantics.

Textual interchange format of FFG is called C-Like Intermediate Format (CLIF).

FFG is generated from an EFSM description and can be in a Tree Form or a DAG Form.

Design

Functional Decomposition

FFGFFGI/O SemanticsI/O Semantics

Architecture Independent

Architecture Dependent

Constraints EFSM SemanticsEFSM Semantics

AFFGAFFG

Refinement Restriction

(Architecture) Function Flow Graph

FFG/CLIF

Develop Function Flow Graph (FFG) / C-Like

Intermediate Format (CLIF) • Able to capture EFSM

• Suitable for control and data flow analysis

EFSM FFGOptimized

FFGCDFG

Data Flow/ControlOptimizations

Function Flow Graph (FFG)

– FFG is a triple G = (V, E, N0) where

• V is a finite set of nodes

• E = {(x,y)}, a subset of VV; (x,y) is an edge from x to y where x

Pred(y), the set of predecessor nodes of y.

• N0 V is the start node corresponding to the EFSM initial state.

• An unordered set of operations is associated with each node N.

• Operations consist of TESTs performed on the EFSM inputs and

internal variables, and ASSIGNs of computations on the input alphabet

(inputs/internal variables) to the EFSM output alphabet (outputs and

internal (state) variables)

C-Like Intermediate Format (CLIF)

Import/Export Function Flow Graph (FFG)

“Un-ordered” list of TEST and ASSIGN operations

– [if (condition)] goto label

– dest = op(src)

• op = {not, minus, …}

– dest = src1 op src2

• op = {+, *, /, ||, &&, |, &, …}

– dest = func(arg1, arg2, …)

Preserving I/O Semantics

input inp;

output outp;

int a = 0;

int CONST_0 = 0;

int T11 = 0;

int T13 = 0;

S1: goto S2;S2: a = inp; T13 = a + 1 CONST_0; T11 = a + a; outp = T11; goto S3;S3: outp = T13; goto S3;

FFG / CLIF Example

(cond2 == 0) / output(a)(cond2 == 1) / output(b)

Legend: Legend: constantconstant, , output flowoutput flow, , dead operationdead operationSS## = State, = State, SS##LL## = Label in State S# = Label in State S#

S1x=x+yx=x+ya= b+c

a=xcond1 = (y==cst1)cond2 = !cond1;

FunctionFlow Graph

S1: x = x + y;x = x + y;a = b + c;a = x;cond1 = (y == cst1);cond2 = !cond1;if (cond2) goto S1L0output = a;goto S1; /* Loop */

output = b;goto S1;

CLIFTextual Representation

Tree-Form FFG

Function/Architecture Optimizations

Function Optimization

Architecture-Independent optimization objective:

– Eliminate redundant information in the FFG.

– Represent the information in an optimized FFG that has a minimal number of nodes and associated operations.

FFG Optimization algorithm(G)

while changes to FFG do

Variable Definition and Uses

FFG Build

Reachability Analysis

Normalization

Available Elimination

False Branch Pruning

Copy Propagation

Dead Operation Elimination

end while

FFG Optimization Algorithm

Optimization Approach

Develop optimizer for FFG (CLIF) intermediate design representation

Goal: Optimize for speed, and size by reducing

– ASSIGN operations

– TEST operations

– variables

Reach goal by solving sequence of data flow problems for analysis and information gathering using an underlying Data Flow Analysis Data Flow Analysis (DFA) framework(DFA) framework

Optimize by Optimize by information redundancy eliminationinformation redundancy elimination

Sample DFA ProblemAvailable Expressions Example

Goal is to eliminate re-computations– Formulate Available Expressions Problem

– Forward Flow (meet) Problem

AE = a+2}

AE = a+1, b+2}AE = a+1}AE = a+1}

AE = AE =

AE = Available Expression

t:= a + 1

S3a := a * 5t3 = a + 2

S2t1:= a + 1t2:= b + 2

Data Flow Problem Instance

A particular (problem) instance of a monotone data flow analysis framework is a pair I = (G, M) where M: N F is a function that maps each node N in V of FFG G to a function in F on the node label semilattice L of the framework D.

Data Flow Analysis Framework

A monotone data flow analysis framework D = (L, , F) is used to manipulate the data flow information by interpreting the node labels on N in V of the FFG G as elements of an algebraic structure where

– L is a bounded semilattice with meet , and

– F is a monotone function space associated with L.

Data Flow Equations

Solving Data Flow Problems

AE = a+2}

AE = a+1, b+2}AE = a+1}AE = a+1}

AE = AE =

AE = Available Expression

t:= a + 1

S3a := a * 5t3 = a + 2

S2t1:= a + 1t2:= b + 2

Solving Data Flow Problems

Solve data flow problems using the iterative method

– General: does not depend on the flow graph

– Optimal for a class of data flow problems Reaches fixpoint in polynomial time (O(n2))

FFG Optimization Algorithm

Solve following problems in order to improve design:

– Reaching Definitions and Uses

– Normalization

– Available Expression Computation

– Copy Propagation, and Constant Folding

– Reachability Analysis

– False Branch Pruning

Code Improvement techniques

– Dead Operation Elimination

– Computation sharing through normalization

Type text

Function/Architecture Co-design

Function Architecture Optimizations

Fun./Arch. Representation:

– Attributed Function Flow Graph (AFFG) is used to represent architectural constraints impressed upon the functional behavior of an EFSM task.

Architecture Dependent Optimizations

libArchitecturalInformation

EFSM FFG OFFG CDFGAFFG

ArchitectureIndependent

EFSM in AFFG (State Tree) Form

F4F3S0

Architecture Dependent Optimization Objective

Optimize the AFFG task representation for speed of execution and size given a set of architectural constrains

Size: area of hardware, code size of software

y = a + ba = cx = a + b

y = a + b

z = a + ba = c

y = a + b

x = a + b

ReactivityLoop

Motivating Example

Eliminate the redundant needless runtime re-evaluation of the a+b operation

Cost-guided Relaxed Operation Motion (ROM)

For performing safe and operation from heavily executed portions of a design task to less visited segments

Relaxed-Operation-Motion (ROM): begin

Data Flow and Control Optimization

Reverse Sweep (dead operation addition, Normalization and available operation elimination, dead operation elimination)

Forward Sweep (optional, minimize the lifetime)

Final Optimization Pass

Cost-Guided Operation Motion

Cost EstimationDesign

Optimization

User Input Profiling

InferenceEngine

AttributedFFG

Relaxed Relaxed Operation MotionOperation Motion

FFG(back-end)

Function Architecture Co-designin the Micro-Architecture

AFFGFFG fsmfsmfsmfsm data f.data f.data f.data f.

II OOcontrolcontrol

datadata

i/oi/o

ASICsASICsprocessorsprocessors

SystemConstraints

SystemSpecs

DecompositionDecomposition

t1= 3*bt2= t1+a

emit x(t2)

Operator Strength ReductionInstruction Selection

Operator Strength Reduction

t1= 3*b

t2=t1 + a

expr1 = b + b;

t1 = expr1 + b;

t2 = t1 + a;

x = t2;

Reducing the multiplication operator

Architectural Optimization

Abstract Target Platform

– Macro-architectures of the HW or SW system design tasks

CFSM (Co-design FSM): FSM with reactive behavior

– A reactive block

– A set of combinational data-low functions

Software Hardware Intermediate Format (SHIFT)

– SHIFT = CFSMs + Functions

ProcessorB

HW4HW3

Macro-Architectural Organization

Architectural Organization of a Single CFSM Task

Task Level Control and Data Flow Organization

Reactive ControllerEQ

a_EQ_b

RESET_a

CFSM Network Architecture

Software Hardware Intermediate FormaT (SHIFT) for describing a network of CFSMs

It is a hierarchical netlist of

– Co-design finite state machine

– Functions: state-less arithmetic, Boolean, or user-defined operations

SHIFT: CFSMs + Functions

Architectural Modeling

Using an AUXiliary specification (AUX)

AUX can describe the following information

– Signal and variable type-related information

– Definition of the value of constants

– Creation of hierarchical netlist, instantiating and interconnecting the CFSMs described in SHIFT

Mapping AFFG onto SHIFT Synthesis through mapping AFFG onto SHIFT and AUX

(Auxiliary Specification)

Decompose each AFFG task behavior into a single reactive control part, and a set of data-path functions.

Mapping AFFG onto SHIFT Algorithm (G, AUX)

foreach state s belong to G do

build_trel (s.trel , s, s.start_node, G, AUX);

end foreach

Architecture Dependent Optimizations

Additional architecture Information leads to an increased level of macro- (or micro-) architectural optimization

Examples of macro-arch. Optimization

– Multiplexing computation Inputs

– Function sharing

Example of micro-arch. Optimization

– Data Type Optimization

ReactiveController

ITE out

Distributing the Reactive Controller

Move some of the control into data path as an ITE assign expression

ITE: if-then-else

Control{1, 2}

T(b+-c-)

Multiplexing Inputs

T = b + c +b

T(b+a)

T(b+c)

Micro-Architectural Optimization

Available Expressions cannot eliminate T2

But if variables are registered (additional architectural information) we can share T1 and T2

T(a+b)

T1 = a + b;x = T1;a = c;

S2T2 = a + b;Out = T(a+b);

emit(Out)

Hardware/Software Co-Synthesis and

Estimation

FFG AFFG

FFG Interpreter (Simulation)

Co-Synthesis Flow

EFSMCDFGSHIFTSHIFT

SoftwareCompilation

ObjectCode (.o)

HardwareSynthesis

Netlist

POLIS Co-design Environment

Programmable Programmable BoardBoard

P of choiceP of choice FPGAsFPGAs FPICsFPICs

Graphical EFSMGraphical EFSM ESTERELESTEREL ................................

CFSMsCFSMs

PartitioningPartitioning

SW SynthesisSW Synthesis

SW Code + SW Code + RTOSRTOS

Logic NetlistLogic Netlist

HW SynthesisHW Synthesis

SW EstimationSW Estimation HW EstimationHW Estimation

Physical PrototypingPhysical Prototyping

Performance/trade-off Performance/trade-off EvaluationEvaluation

CompilersCompilers

POLIS Co-design Environment Specification: FSM-based languages (Esterel, ...)

Internal representation: CFSM network

Validation:

– High-level co-simulation

– FSM-based formal verification

– Rapid prototyping

Partitioning: based on co-simulation estimates

Scheduling

Synthesis:

– S-graph (based on a CDFG) based code synthesis for software

– Logic synthesis for hardware

Main emphasis on unbiased verifiable specification

Hardware/Software Co-Synthesis

Functional GALS CFSM model for hardware and software

initially unbounded delays refined after architecture mapping

Automatic synthesis of:

• Hardware

• Software

• Interfaces

• RTOS

ResourcePool

CFSMNetwork

RTOSSynthesis

HW/SWSynthesis

PhysicalPrototyping

RTOS Synthesis and Evaluation in Polis

1. Provide communication mechanisms among CFSMs implemented in SW and between the OS is running on and HW partitions.

2. Schedule the execution of the SW tasks.

a := a + 1a := 0

detect(c)a<

emit(y)

266341

Estimation on the Synthesis CDFG

Architecture Evaluation Problem

BehaviorBehavior

ArchitectureArchitecture

HDLHDLHighHighCostCost

Out ofOut ofSpecSpec

SystemSystemBehaviorBehavior

Refinee

SystemSystemArchitectureArchitecture

Refinee

Time and MoneyTime and Money

Proper Architectural Evaluation

Time and MoneyTime and Money

Refinee

In SpecIn SpecLow CostLow Cost

BehaviorBehavior

ArchitectureArchitecture

ImplementationImplementation

Network ofEFSMs

SW Estimation

SW Estimation HW EstimationHW Estimation

HW/SW Co-SimulationPerformance/trade-off Evaluation

HW/SW PartitioningHW/SW Partitioning

Estimation-Based Co-simulation

Co-simulation Approach (1)

Fills the “validation gap” between fast and slow models

– Performs performance simulation based on software and hardware timing estimates

Outputs behavioral VHDL code

– Generated from CDFG describing EFSM reactive function

– Annotated with clock cycles required on target processors

Can incorporate VHDL models of pre-existing components

Co-simulation Approach (2)

Models of mixed hardware, software, RTOS and interfaces

Mimics the RTOS I/O monitoring and scheduling

– Hardware CFSMs are concurrent

– Only one software CFSM can be active at a time

Future WorkFuture Work

– ArchitecturalArchitectural view instead of component view view instead of component view

Research Directions in F-A Codesign

Functional decomposition, cross- “block” optimization ~ hardware/software partitioning techniques

Task and system level algorithm manipulations ~ performing user-guided algorithmic manipulations

chapter 7 function-architecture codesign paradigm

optimization codesign

optimal function

application function

control flow

architectural information

architectural units

control data flow analysis

optimal match

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