chapter 2 static errors testing of adc 2.1...
Post on 27-Jun-2020
28 Views
Preview:
TRANSCRIPT
36
CHAPTER 2
STATIC ERRORS TESTING OF ADC
2.1 PREAMBLE
Data converters are used in a wide variety of electronic systems, as
they provide the interface between analog and digital signals. Analog to Digital
Converters should possess linear response so as to perform the conversion
efficiently. In order to ascertain the same, the data converters are to be tested.
Determination of static errors linked to the deviations in the converter’s transfer
function is the vital link in the testing of converters. Differential nonlinearity
error (DNL), Integral nonlinearity error (INL), gain error (GE) and offset error
(OE) are the important static error parameters in the testing process.
The gain error and offset error in analog to digital converters are
relevant in applications requiring matched converters such as interleaving,
simultaneous sampling, and I/Q signal processing, where there is a need to match
relative gain and offset between the individual converters (Walt Kester 2004).
These two errors can be compensated by providing appropriate biasing. They
invariably do not affect the electronic system in which the converters are used.
However, The INL error and the DNL error affect the linearity of the converters
significantly (Blair et al 1994). IEEE standards 1241-2000 and 1057 give the
static parameters of typical converters along with their performance in respect of
different applications. Integral non linearity and differential non linearity are most
37
important in data transmission, video and picture transmission and in medical
applications. Analog signal from the standard sources is required for testing the
linearity of ADC. The digital outputs from the ADC under test are then post-
processed by the test circuits to determine the static errors associated with it.
The automatic test equipment (ATE) and built in self test (BIST) are
the commonly used test techniques and they use histogram based test procedure
to determine the static errors of an ADC (Ginetti et al 1991), (Carbone et al 1998),
(Max et al 2001), (Alegria et al 2002).
2.2 ADC STATIC ERROR TESTING
Doernberg et al (1984) presented a computer-aided ADC
characterization method based on the code density test and spectral analysis using
the Fast Fourier transform. The code density test produces a histogram of the
digital output codes of an ADC, sampling a known input. The code density can be
interpreted to compute the differential and integral nonlinearities, gain error,
offset error, and internal noise. The method involves numerous iterations and
does not deal with extreme input values. Also it consumes more memory, time
and hence cost.
Bakirov et al (1985) proposed a method to characterize the ADC using
look back test. The method gives a test code to the DAC and its output is given as
an input for the ADC. The code comparator compares the output of the ADC with
the input given to the DAC and determines the error in the ADC. The error in the
DAC is not incorporated in the evaluation of the error function.
38
Max (1989) proposed a servo based complete ADC test. The digital
circuitry generates an error signal, which is ramped up using integrator. The ramp
output is given to ADC, whose output is connected to the digital circuit, there by
generating an error signal. The inherent drawback is that the process is manual.
Ram bobba et al (1990) proposed that embedded analog-to-digital
converters in microcontrollers be tested with a digital VLSI test bench as an ATE,
using the principle of tally array. The sampled data is stored in an array of huge
memory, and the tally in the occurrence of each test input is computed, and there
by the errors are determined. The method of tally array requires more samples
and memory to test the ADC and consumes more time and cost.
Pei et al (1991) proposed a method for testing the static characteristics
of ADC using sinusoidal signal as input. The difference between the input and
output in the frequency domain was used to obtain the values of INL and DNL.
Finding static errors through frequency domain involves numerous computation
cycles.
Ginetti et al (1991) presented a statistical method for characterizing
ADC using Gaussian noise as the test stimulus for the histogram test. The error in
the measurement of maximum INL and the number of samples needed for the test
procedure are high. Further, to characterize the ADC, a high speed DAC is
required.
Blair J (1994) presented a result concerning the measurement of DNL
and INL of ADC's using the histogram method with a sinusoidal input signal. The
harmonic distortion of the applied signal is analyzed; the noise floor in the
39
analysis measures the errors. The method assumes a mixture of coherent and
random sampling rather than pure random sampling.
Irons et al (1996) enumerated in his paper that, a given calibration data
set may be used to estimate the specific error performance features pertaining to
ADC architectural considerations. The procedure requires proper selection of
basis functions based upon properties of a desired feature to characterize the
ADC.
Capofreddi et al (1997) proposed a linear modeling technique applied
to three common methods for testing analog-to-digital converters, the servo-loop
method, the tally-and-weight method, and the code density method-to improve
their efficiency and accuracy. Since the linear model may itself introduce error in
the estimates, the accuracy of the model must be determined in order to make the
comparisons meaningful.
Mehdi Ehsanian et al (1998) developed a BIST for testing ADC using
DAC as loop back for the source signal of ADC. The BIST structure has a
compromise between test accuracy, area overhead and test cost.
Martins et al (1999) proposed a method of testing with noise sequence
as an input. It is a variant of the histogram test where Gaussian noise is used as a
stimulus signal. Though the methodology allows for an automated and extensive
characterization of analog-to-digital converters, it is computationally complex.
Renovell et al (2000) proposed a reduced hardware for histogram based
BIST procedure, to test the static errors of ADC. The overdrive of the ramp signal
40
leads to higher number of occurrences in extreme codes which occupies more
memory.
Azais et al (2001) investigated the viability of an ADC BIST scheme
for implementing the histogram based testing technique. The approach extracts
the ADC parameters from the histogram. A triangular wave input signal
combined with an appropriate time decomposition technique is used for the test
procedure. The method does not investigate the requirement of the memory to
store the extreme code occurrences.
Adamo et al (2001) proposed that, the A/D converter transfer function
was approximated by a chebyshev polynomial and the INL is estimated from the
FFT. Though the method reduces the test time significantly, they are inaccurate
for the measurement of specifications such as maximum INL and DNL.
Alegria et al (2002) presented a histogram based method using small-
amplitude triangular waves for the quasi-static testing of analog-to-digital
converters. In this test procedure, closed-form relations for designing the test as
well as for its characterization in terms of efficiency and uncertainty are provided.
The generation for quasi-static triangular source is not discussed and it is
cumbersome to design.
Olleta et al (2006) presented Dynamic element matching approach to
ADC testing. With this technique a nonideal DAC is used to generate an
excitation for the ADC under test. Dynamic element matching is used to create
an excitation from imprecise components. The error due to DAC will be
inherently associated with errors in the ADC under test.
41
Testing of ADC based on a linear model has been proposed (Jin et al
2003), (Adamo 2001), (Capofreddi et al 1997), and (Cherubal et al 2003). These
test methodologies are based on exploiting the correlations between the code
widths of different codes of an ADC. A linear model that relates all the code
transition edges to a few set of independent parameters is constructed through a
set of statistical measurements across a large number of devices. The number of
parameters used to model the ADC is significantly smaller than the number of
converter output codes. Thus, static non-linearity testing of the ADC requires
measurement of fewer numbers of unknowns and hence reduced test time.
Michaeli et al (2005) proposed a model based ADC test technique,
which models INL of an ADC as a superposition of low-frequency and high-
frequency components. Identification of low-frequency components is done using
the spectral analysis and they reveal general shape of INL plot. Identification of
high-frequency components reveals the major discontinuities in the INL plot and
this is done by measuring the DNL of specific codes. The results indicate that the
proposed method can track the shape of the INL plot, though a significant error in
the estimation of INL exists.
Wen-Ta Lee et al (2008) proposed a new high precision ramp
waveform generator for low cost ADC test. Combined with histogram analysis,
an ADC can be easily tested on general digital testers. This approach uses FFT
for computing noise floor and hence the data converter’s non linearity errors.
Jianguo Ren et al (2008) proposed a histogram BIST scheme for static
testing of ADC. For a monotonic ADC, the output codes have an approximate
stair-like relationship proportional to the input signal. Based on this property, a
42
space decomposition technique is proposed to reduce the testing time. By
utilizing this technique, ADC’s static parameters can be estimated in shorter
testing time with low hardware overhead.
Korhonen et al (2010) proposed a method to test the integral
nonlinearity of ADC without an accurate test stimulus, but only constant dc offset
between two low-quality test signals. A generator for producing the constant
offset is proposed and its limitations are analyzed. The proposed offset generator
is used in a ratiometric test setup that influences a reference voltage drift. The
offset error is added with test signal so that full scale error can be tested. The
method uses loop back DAC to test ADC. Though method addresses BIST testing
of ADC in ratiometric mode, it uses Automatic test equipment principle and not
BIST.
2.3 ISSUES IN BIST FOR ADC TESTING
The above discussed methods for testing static error in the ADC are
mainly based on histograms or on frequency domain analysis. Few of these
methods are based on the concept of loop back in which the output of ADC under
test is fed back to DAC and its output is compared with test signals so as to
measure the error in ADC.
Figure 2.1 shows the block diagram of a generic histogram based
method. It consists of a waveform generator and a digital response analyzer along
with ADC under test. A ramp or sinusoidal signal is given to the ADC under test
with a known set frequency and the ADC is triggered to sample the data with
predefined sampling frequency. The response analyzer counts the occurrence of
each output code of the ADC under test and stores the occurrence value in the
43
memory. From the occurrence value of each code, the static errors are computed.
Figure 2.1 Generic Histogram BIST
The issues in this class of methods are that the method needs multiple
test runs to get the required accuracy in measurement. The response analyzer
should be run at a speed of higher than the sampling speed of the ADC under test.
Hence DSP engines are used in practice. The error computed by finding the
deviation between practical and ideal occurrence. Choosing the ideal occurrence
value for the computation of error is critical because of the set input and sampling
frequency.
Figure 2.2 shows the block diagram of a generic Loop back testing
method. It consists of a signal source, a tested ADC, a DAC and a micro
processor along with the ADC under test. The ramp or sinusoidal signal with
known set frequency is given to the tested ADC and ADC under test. These two
ADCs are triggered to sample the data at defined sampling frequency. The
microprocessor analyzes the magnitude of the input signal and that of the ADC
under test and hence computes the static error.
44
Figure 2.2 Generic ADC test using DAC
The use of additional data converters in the loop back test method is
considered to be the dominant limitation in testing of ADC. Further, the errors of
the additional data converters might add to the error of ADC under test. In this
chapter a novel time tick BIST method for ADC’s static error testing by
addressing the above mentioned issues.
2.4 PROPOSED TIME TICK BIST METHOD ADC STATIC
ERROR TESTING
The block diagram of the proposed Time Tick BIST (TTBIST) method
is given in Figure 2.3. A ramp signal is fed into ideal ticks counting module, the
slope conditioning module and the ADC under test. The ideal ticks counting
module determines the ideal time tick count value for specific input signal. Slope
conditioning module detects the slope of input ramp signal. A switch S routes
reference voltage to ADC under test by way of alternating between ratiometric
mode and single ended mode. The single ended mode is constant reference
voltage (VREF1) is provided to the ADC under test, where as in ratiometric mode,
45
a falling reference (VREF2) for a rising input voltage is provided to ADC under
test. Practical digital code generated, by the ADC under test for each transition is
sent to the exploitation module. The exploitation module also receives a pre-
loaded code. This module counts the number of ticks for every code transition
until the received code is equal to the pre-loaded code. The measured time ticks
for each code transition are updated in the memory instantaneously.
It is essential to note that the ideal Least Significant Bit (LSB) value of
ADC is usually theoretically computed values in most other testing methods. But
in this proposed method, the ideal LSB value is dynamically measured every time
when ADC testing begins and the value is stored in ideal ticks register so as to
minimize the probability of error in the measurement due the error in ideal value.
Figure 2.3 Block diagram of TT BIST
Practical
Code
Pr e Loaded
Code (1)
Exploit at ion
Module
Memory
Regist er
RAMP
Sour ce ADC
Slope
Det ect or
I deal
Ticks
Regist er
Slope condit ioning
Module f or
Rat io met r ic
ADC
1
I deal t icks Count ing Modules
Vin
V ref
S Fs (Sampling clock)
2 Vref f or single ended
46
2.4.1 Ramp Source
The conventional ramp signal generation methods reported in the
literature include the ramp generators for mixed-signal (Na Zhang et al 2003),
SSLAR ramp signal (Sakkarapani et al 2009), adaptive ramp generators (Azaïs
et al 2001), and high precision ramp generators (Wen-Ta Lee et al 2008). The
slope of the ramp in these generators depends on the passive devices used in those
circuits. But in this method, a digitally switchable ramp signal generator has been
proposed to generate ramp signal with dynamically switchable slopes for ADC
testing having varying accuracy. In this method, the current sources are digitally
controlled to have different ranges of current which are used for generation of
variable slope ramp signals. The expressions for the collector current, slope of the
ramp generated are expressed as.
t
fsV
RampC
IC
(2.1)
rampC
cI
m (2.2)
Assuming ‘n’ number of current sources it is expected that there would
be 2n-1, combinations of resulting current. The variation in these currents will in
turn manifest as the variation in slope of the ramp signal.
If the time taken by a ramp to produce a digital transition in the output
of the ADC is T, then the frequency of the ramp is maintained such that
1/ T < CLK_TT / N where CLK_TT is the free running clock frequency which is
supplied as clock to CNT_ TTP and N is the precision tune factor of the error
estimate.
47
Figure 2.4 Digitally Switchable Ramp source
2.4.2 Ideal Ticks Counting Module
The ideal ticks counting module counts the ticks corresponding to the
LSB value of the ADC by the ramp input. It consists of slope detection circuit and
an ideal time tick counter to store the ideal ticks count value (CNT_ TTI). The
slope detection circuit consists of lower threshold (Vlt) and upper threshold (Vut)
comparators. It obtains the slope of the ramp signal by detecting Vut and Vlt levels
of the ramp signal.
The voltage difference between Vut and Vlt is maintained as VLSB and
estimates the ideal time ticks (TTI) for a LSB value in the counter. When the
ramp is in between the thresholds (Vut and Vlt), the enable clock (EN_C) signal is
provided with a high logic signal, which will enable CNT_ TTI to count the free
running clock (CLK_TT). From the CNT_ TTI value obtained the ideal time ticks
(TTI) are computed using
48
ltV
utV
refV
nI
TTCNT
ITT
12
_ (2.4)
When the ramp signal exceeds Vut then the ideal time tick counter
CNT_TTI is disabled as shown in Figure 2.5.
Figure 2.5 Slope Detection Circuit
The algorithm for measuring the ideal time ticks of the ADC for the
ramp signal is a pseudo code as given in Figure 2.6.
Figure 2.6 Pseudo Code for TTI
Vin (Analog
input )
CLK_TT
Vlt _o
CNT_ TTI
(Ideal ticks
counter)
EN_C
+
+
Vlt
Vut
Vut _o
TT_total=0
Wait until EN_C=1
While EN_C=1
CNT_ TTI ++
End loop
TTI= (CNT_ TTI * k) / (2n-1) // k = (VREF/(VUT-VLT))
49
2.4.3 Slope Conditioning Module for Ratiometric ADC
In the traditional ratiometric test by varying the unknown resistance
value the difference between reference and input voltages at the output of an
ADC (Russel et al 2004).
In a traditional ratiometric test, an ADC is used to measure the
unknown resistance in a circuit. The input to the ADC is a reference voltage and
an input voltage. The reference voltage has to be varied according to the variation
of unknown resistance. The output of ADC as a function of the difference
between VRef and Vin will represent the resistance ratio and hence the unknown
resistance as the resistance value is known.
However, varying the unknown resistance and hence providing varying
VRef as input to ADC has been problem. Under such circumstances, a slope
conditioning module as described below (Figure 2.7) has been designed and
implemented.
To provide a varying input, a rising ramp signal is given to the slope
conditioning module as well as an analog input to the ADC (Figure 2.7). The
slope conditioning module converts rising input in to a falling ramp, this falling
ramp signal is added with a full scale voltage. The slope conditioning module
keeps the voltage at the point Z (vref ) as vin + vref = VFS of the ADC at any
instance of time.
Voltages at input and output of slope conditioning module is given is
Figure 2.8. The voltage at point X represents the input voltages being fed directly
to ADC and also to an inverter. The voltage at point Y is the output of the
50
inverter. This voltage is passed through an adder with a full sale voltage (VS) to
obtain a triangular voltage at Z which is then fed to the ADC along with Vin.
Figure 2.7 Ratiometric signal conditioning circuit
Figure 2.8 VREF and VIN generated from circuit in Figure 2.7
2.4.4 Exploitation Module
The functional blocks of the exploitation module is shown in Figure
2.9. It controls and coordinates the overall operation of the proposed BIST. It
consists of digital comparator, reference counter, logic gates, practical ticks
counter (CNT_TTP) and a latch.
Vs
( Full scale volt age)
Volt age at point Z
(Vref =Vs-Vin)
Volt age at point X
(Vin)
Volt age at point Y
(-Vin)
51
The digital comparator has its input from the output of ADC (D) and
reference counter (C). The comparator output is high when C is less than D and
output is low when C is equal or greater than D. The reference counter is initially
set to a value one which is greater than the ADC’s initial value. The active high
output of the digital comparator enables the practical time tick counter
(CNT_ TTP) to count the free running clock (CLK_TT). When C is equal to D,
the digital comparator disables the time tick counter from the process of counting
the free running clock. The time ticks value of CNT_ TTP is latched after each
conversion in a cycle. The latched TTp (i) is stored in the memory. A delay-buffer
provides minimal delay for the latch to capture each TTP (i) and then CNT_ TTP
is cleared (CLR) to zero to facilitate the next counting TTP (i). Further, the digital
comparator enables the reference counter to increment the next value of D there
by the system is ready for counting time ticks for next code. This process is
repeated till the full scale of the ADC is reached.
Figure 2.9 Exploitation Module
CNT_TTP
Pr e-load
value (1)
CLK_TT
D<C
Ref er ence
count er (i)
I nput
f rom
ADC
TTp(i)
D (0…N-1)
C (0…N-1)
Delay Buf f er
Digi t al
Compar at or
Lat ch
52
The Pseudo code for calculation of TTp(i) for all the above calculations
is given in Figure 2.10.
Figure 2.10 Pseudo code for TTp (i)
2.5 STATIC ERROR PARAMETERS COMPUTATION
In the proposed method the ADC output occurrence are measured in
terms of time ticks and all static error parameters are computed from the time
ticks
The ideal time of the ramp input signal to attain a LSB value of the
ADC is given as
SecondsR
T
FSV
LSBV
IdealT (2.5)
Where, VLSB is the step size of the ADC, TR is the time period of the
ramp signal, and VFS is its full-scale voltage of the ADC.
Ref_counter = 1
TT_counter = 0
Wait until EN_C = 1
ADC_value=getValue_ADC ( )
i = 0
While (ADC_value < 2n-1)
{
ADC_value=getValue_ADC( )
If Ref_counter>ADC_value then
CNT_TTP(i)++
Else
{
TT_P (i) = CNT_TTP(i)++
CNT_TTP(i)++
Ref_counter++
i++
}
} End Loop
53
Hence, the number of time ticks per ideal digital transition of the ADC
with respect to sampling frequency is given as
idealT
sF
ITT (2.6)
Let TTP (i) be the number of practical time ticks obtained for every ith
code transition by the proposed method and the error factor ei of the ith code, can
be calculated as
iTTi
pTT
ie )( (2.7)
The static error parameters of the ADC is computed from the practical
time ticks TTP (i) and ideal time ticks TTi as given below. The values for each
count furnish the DNL error as
iTT
iTTi
pTT
iDNL
)(
)( (2.8)
The INL error value for the ith code transition is
)()1()( iDNLiINLiINL (2.9)
Gain error can be calculated as the full-scale error minus the offset
error. Full-scale error is the difference between the actual (practical) value that
triggers the transition to full-scale output of ADC and the ideal (theoretical)
analog full-scale transition of the ADC.
The number of time tick for the ramp to sweep the full-scale range
for an ideal ADC is given as
54
nTT
FTT I
IDEAL
2 , where n is the resolution of the ADC in bits. The
full scale error is calculated using the formula
ITT
IdealFTTTT
Fe
F _ (2.10)
TTF is the CNT_ TTI time tick value for the ADC to reach the full scale
digital output for the given ramp input. Gain error may thus be found as,
)(IDNLF
eE
G (2.11)
DNL error for the first code of ADC under test is an offset error of that
ADC.
2.6 RESULTS AND DISCUSSION
The proposed Time Tick BIST has been implemented in hardware as
shown in Figure 2.11. The exploitation module, slope detection circuits, time tick
counter, and the memory have been coded in the verilog and realized in ALTERA
FPGA board (DE1). The ramp generator, signal conditioning circuit and threshold
detector have been realized on vero board. A 12 bit MAX162 ADC has been
chosen as the ADC under test. The data and control bus of the ADC are
connected to the FPGA through GPIO pins provided in ALTERA board.
The IEEE 1241-2000 standard specifies that a data converter is
permitted to have a quantization error resolution between -0.5 LSB and +0.5
LSB. In conventional histogram based methods the error resolution is reported to
be 0.01 LSB. In order to validate the proposed TTBIST method, an error
55
resolution of 0.05 LSB has been chosen. Hence a 20 time tick (1/0.05 LSB) has
been chosen as the ideal tick.
Thus, for the given specification the MAX162 ADC output obtained at
a sampling frequency of 5100 KHz, with number of time ticks, TTIdeal = 20 ticks
for a 1Hz ramp signal, is used in all further calculations.
Figure 2.11 Experimental setup for Testing ADC MAX162
The output of the 12-bit ADC MAX162 for all possible input was
measured manually. The DNL and INL errors were calculated by
conventional method (Mark Burns et al 2001). Figure 2.12 shows the plot for
differential non linearity error of the ADC under test, estimated by the
conventional method and Figure 2.13 shows the plot for integral non linearity
error of the ADC under test.
56
Figure 2.12 DNL Error Values Estimated by Histogram Method for
MAX162 up to CODE 200
Figure 2.13 INL Error Values Estimated by conventional Method for
MAX162 up to CODE 200
The time ticks generated by the test input codes of the MAX162 ADC
pertaining to the proposed TTBIST are given in Figure 2.14. The corresponding
57
DNL Error and INL error computed from the time ticks generated for the input
codes are given in Figure 2.15 and 2.16 respectively. The difference between the
INL error from the proposed TTBIST and those from the conventional method
are shown in Figure 2.17.
Figure 2.14 Time Tick Values for MAX162 up to CODE 200
Figure 2.15 DNL Error Values for MAX162 up to CODE 200
58
Fig. 2.15 INL Error Values for ADC0804 up to CODE 200
Figure 2.16 INL Error Values for MAX162 up to CODE 200
Figure 2.17 Error Estimation Difference Between TT BIST and
Histogram Method
59
In order to validate the proposed TTBIST procedure, the Static
errors such as Offset error, gain error and INL error were compared against
the values obtained by histogram method as shown in Table 2.1.
It is observed that the INL error computed using the proposed method
is closer to conventional method by 98.33%
Table 2.1 Comparison of obtained values using TT BIST
with Histogram method
To validate the proposed TTBIST, the test time of the methods are
tabulated in Table 2.2 along in the unit of proposed method.
In Histogram BIST testing time of time decomposition method and
space decomposition method is calculated using (Jianguo et al 2001)
n
sF
idealH
Itest
T 2 (2.12)
Where Fs is the sampling frequency, denoting the number of bits under
test, Hideal is the number of iterations considered for offset gain and INL errors. In
Static Errors
TTBIST
method
(in LSB)
Histogram
method
(in LSB)
Offset Error +3.5 +3.8
Gain Error +9.35 + 9.42
INL Error -0.32 - 0.3
60
the proposed TT BIST all three parameters are observed in single cycle. The
testing time of proposed method TT BIST satisfies
n
sFproposedtest
T 232
_ (2.13)
Table 2.2 Comparison of Testing Time
Testing TimeTesting Method
Bits of
ADC (n) Fs=10MHz Fs=20MHz Fs=50MHz
8 500 ms 250 ms 100 ms
10 7.5 s 3.8 s 1.5 sTime Decomposition
12 2 min 1 min 24 s
8 2400 us 1200 us 480 us
10 9600 us 4800 us 1920 usTime and Space
Decomposition12 38.4 ms 19.2 ms 7.68 ms
8 800 us 400 us 160 us
10 3200 us 1600 us 640 msThe Proposed TTBIST
12 12.8 ms 6.4 ms 2.56 ms
It is observed that the testing time for the testing a 12 bit ADC using
proposed method is lesser than the testing of the same ADC in conventional
methods.
2.7 CONCLUSION
The proposed method converts an Analog to Digital converter output
into corresponding time ticks. The conventional histogram BIST method needs
higher number of iterations and computations, but the proposed TT BIST method
61
needs only one test run for accurate and better results for computation of the
non-linearity error. It is important to note that, in the histogram method, the input
signal often produces an overdrive resulting in higher extreme code occurrences,
but such a similar situation is averted in TT BIST, since the ticks counter will be
stopped when signal reaches the full scale level. It is observed that the testing
time for the proposed method is lesser than the conventional methods. This test
scheme could be executed every time when SoC starts up, providing up-to-date
error characteristics and non-linearity of an ADC.
top related