cec 450 real-time systemsmercury.pr.erau.edu/~siewerts/cec450/documents/... · – multi-threaded...

August 29, 2019 Sam Siewert

CEC 450Real-Time Systems

Lecture 1 – IntroductionPart 2

Questions on Final Projects?Examples here -http://mercury.pr.erau.edu/~siewerts/cec450/documents/Video/– Creative Projects - Duck Hunter, Robotic arms, Tilt/Pan trackers, etc.– Standard Project - 1 Hz, 10 Hz Clock Image Capture and Processing

Verifies well -http://mercury.pr.erau.edu/~siewerts/cec450/documents/Video/Appendix6_1Hz_Samples.zipHas glitch -http://mercury.pr.erau.edu/~siewerts/cec450/documents/Video/CLOCK.zip

Choose Standard or Creative in Ex #5 and start

Complete first try, testing, and report in Ex #5

Debug during last week of class

Demonstrate for Final Exam

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Questions on Ex #1?Follow Ex #1 submission guidelines - I may build and run, but report so I don’t need to, and comment so you can walk-through confidently

Turn in on Canvas Next Week Friday

For coding standards, pick one and follow - RTES are most often C code and ASM (Lewis book). C is old, but still favored for OS kernel and ES firmware -standards for C: Ganssle or similar CMU, GNU or NASA guides.

If you must code in C++ (for good reason like OpenCV or ROS, or OS-X kernel and drivers, etc.) then use Google C++ or Stroustrup.

You can complete this course using nothing but simple C

Focus is on predictable response - this will take some time to master!

Theory, practice (with services as threads or tasks) and careful design are required for ultimate success. This is practice - do your best and I will help you improve - points on practice exercises are based on:

– Completeness– Thoughtfulness (be honest, ask questions if you get stuck, what works, what does not)– Good documentation for repeatability - like you would submit to QA– Makefile, report as doc or PDF (in format of how you tested), and zip up code

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NUC/Jetson Linux - Go To Lab, Verify LoginOption #1 – Use King 122 NUC / Jetson Lab– Learn Host and Embedded Linux– Getting Started– Jetson - Used for Self-Driving

Cars– NUC - Way Cool!ssh -X ubuntu@192.168.122.122– [from Host 121]

Optoin #2 - Raspberry Pi 3b+– $80 kit– You own it, can be used for

entire course

Dev Option #3 – Virtual-Box Linux with Ubuntu 16.04 LTS– Use Windows or Mac PC– Learn Linux, it’s Easy– Real-time Testing must be done

on native Linux Sam Siewert 4

Questions on Lab Resources?B72-122-NUC1 [192.168.122.111] => B72-TK1-112 [192.168.122.112]

…

B72-122-NUC9 [192.168.122.191] => B72-TK1-192 [192.168.122.192]

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Left Side - #1 to #4

#5 & #6

Left Side - #7 to #9

Downloading and Copying FilesGetting Files to NUC– Option #1 - Bring files to Lab

on USB Memory Stick, Plug into NUC (or Jetson)

– Option #2 - Download files from NUC Web browser (right click, Save-Link-as)

– Option #3 - Put files on a Shared “P:” Windows drive and access from NUC

Getting Files from NUC to Jetson (Testing)– Use “Connect to Server” from

“Places” and use SSH to Jetson IP, using “ubuntu”, “ubuntu”

– Drag and drop files from NUC folder to Jetson folder

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Now Drag and Drop Files on NUC Desktop

Transfer files to/from NUCTake code with you on memory stick or copy to P: drive before you leave (backed up)Remove test files from JetsonCompile code native on Jetson (like PRClab)Possible to cross-compile, cross-debug if you want with NVIDIA tools

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RT TerminologyFirmwareEmbedded SystemsReal-Time Theory and Practice

See -http://mercury.pr.erau.edu/~siewerts/cec450/documents/Lectures/Terminology.pdf

Also in Book (Notes) in Appendix

For all S: Ci, Ti, Di, Compute U, m=number of S

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)12()/(1

1

−≤=∑=

m

i

mmTiCiU

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Typical RTOS Scheduling PoliciesFixed Priority Preemptive– Tasks State Based on Resources Required

Needs CPU Only = ReadyNon-CPU Resource Required = Pending

– Task Context Switch on System Call or Interrupt – Dispatch from Ready Queue

– Dispatch with Rate Monotonic Priority– RM LUB Feasibility– Feasibility Tests

Scheduling Point AlgorithmCompletion Test AlgorithmOver LCM of Periods

Dynamic Priority Premptive– Earliest Deadline First– Least Laxity First

delayedreadypending

Suspended,+Delayed,+Pending

executing

Dispatch

Yield(taskDelay())

Wait onResource

(semTake(),pause())

Interference(preemption)

Suspend(unhandled exception,

taskSuspend())

Note: Different from Chapter 7In VxWorks Kernel

Programmer’s Guide

POSIX RT Task ExampleS1 – Computes Fibonacci for 10 milliseconds and quitsS2 – Computes Fibonacci for 20 milliseconds and quitsC1=10, C2=20 millisecondsT1=D1=20 & T2=D2=50 milliseconds

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https://www.mathsisfun.com/numbers/fibonacci-sequence.html

CPU Loading = ____ %

Feasible Schedule?

Safe? Easy to Emulate?

Violates Rate Monotonic Feasibility Test?

)12()/(1

1

−≤=∑=

m

i

mmTiCiU

What Does Theory Tell Us?Look over LCM of Periods (J Lehoczky, L Sha, Y Ding)If Schedule Feasible over LCM, Feasible for All Time

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Example 5 T1 2 C1 1 U1 0.5 LCM = 10T2 5 C2 2 U2 0.4T3 10 C3 1 U3 0.1 Utot = 1

RM Schedule 1 2 3 4 5 6 7 8 9 10S1S2S3EDF ScheduleS1S2S3TTDS1 2 X 2 X 2 X 2 X 2 XS2 5 4 3 2 X 5 4 3 X XS3 10 9 8 7 6 5 4 3 2 1LLF ScheduleS1S2S3LaxityS1 1 X 1 X 1 X 1 X 1 XS2 3 2 2 1 X 3 3 2 X XS3 9 8 7 6 5 4 3 2 1 0

Questions to Ponder …What Does Theory Tell Us?

Can We Emulate the Fibonacci Workload Accurately– In Linux?– In FreeRTOS?– With VxWorks - hint, hint - here’s a VxWorks solution– With an ISR and Interrupts Asserted by a Programmable Interval

Timer?– Or a timing sequencer that gives semaphores to services? -

Example

What are Pitfalls? - Linux common mistakes

Why Would I want to Do This? Sam Siewert 12

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Complex Multi-Service SystemsMultiple Software Services (Dynamic Admission – Reconfigurable)Synchronization Between ServicesCommunication Between ServicesMultiple Sensor Input and Actuator Output InterfacesIntermediate IO, Shared Memory, Messaging

Ph.D. Dissertation, CU Boulder, January 2000

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Multi-Service PipelinesRT Management

tBtvid(30 Hz)

Bt878 PCINTSC decoder

(30 Hz)Serial A/B ISA ethernet

frameRdyinterrupt

RGB32buffer

tFrmDisp(10 Hz)

grayscalebuffer

tFrmLnk(2 Hz)

tNet(2 Hz)

frame

TCP/IP pkts

Event releases / Service control

tOpnav(15 Hz) tTlmLnk

(5 Hz)

tThrustCtl(15 Hz)

tCamCtl(3 Hz)

P0

P1

P2

P3

SWHW

frameRdy Control Plane

Data Plane

RemoteDisplay

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Why are RT Embedded Systems a Challenge?– Real-Time Services – Correct Results on time – Deadlines!

Multi-service Concurrency Required, for Software, Multi-threaded– Multiple interfaces to service in addition to data processing– Multi-threaded compared to Main Loop + ISR Executive– Supports RT analysis and design (Rate Monotonic)

Function/Service Allocation – HW Service Off-loadManagement of CPU, IO, and Memory Resources

– CPU ResourceModern architecture – high throughput, less deterministicpipelines, super-scalar, branch prediction, VM, split-transaction and burst transfer bus interfaces, multi-level caches

– I/O Interface ResourcesSensors / Actuators (Interaction with Real World)Networks (Latency and QoS)Off-load and Memory Devices (e.g. Flash, FPGAs, DSP)

– Memory Hierarchy ResourcesRegister file, L1/L2 cache, SRAM, dynamic RAM, Flash

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How to Make RT Embedded Systems Easier!RT Service and CPU Resource Management– RT Theory, Practice, and Pitfalls (Theory -> System)

RMA and DMA Resource TheoryPrediction and Measurement of PerformanceWhen to Allocate Services/Functions to HW, FW, or SW

– Multi-threaded RTOS SystemsDesign Methods (DFD, SDL, EFSM and MSC methods)RTOS Mechanisms (e.g. message queue, signal, semaphore)Analysis Tools (e.g. Windview)HW/FW Debug Tools (e.g. ICE / JTAG)

I/O Device Interfaces and Drivers– Abstracted SW-HW Interfaces– Interaction with Memory System (MMIO, DMAs, Plug-n-Play)

Memory Hierarchy Analysis and Abstraction– Multi-level Cache Performance Models– Abstracted Non-Volatile Memory Filesystems

So Why SW for HRT Systems?ASIC and FPGA State-Machine Solutions Offer Hardware Clocked Deterministic Solutions

FPGAs Can be Updated with New Bit-streams (Synthesized HDL to Reconfigurable Logic Elements)

Software (Firmware) Remains Simplest for Field Upgrade (Reconfigurable at Run-time)

FPGAs Can be Costly Per Unit

Cost of Software Engineering vs. Hardware Engineering

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