architecture advanced s3
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Advanced Computer Architecture July 2012 Anant Gopal Joshi 000
Advanced Computer Architecture S1
Anant Gopal Joshi
Session 3
July 2012
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Problem 1.6
Program Computer A Computer B Computer C
Program 1 1000 100 50
Program 2 1 10 50
Program 3 2 1 20
Program 4 10 1.25 10
Average 253.25 28.0625 32.5
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MIPS = (Number of Instructions / Time of Execution) / 1000000
For Program 1, Computer A MIPS = (1000000000 / 1 ) / 1000000
= 1000
For a Instruction mix of Program 1 Computer A performs best Average MIPS ranking is Computer A , Computer C and Computer B
Computer C gives a uniform performance, Computer B comes next
Computer A is some special purpose machine
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Problem 1.7
SIMD is a vector processor while MIMD is multiprocessor organization
SIMD executes one program MIMD executes multiple programs
UMA All the processors have Uniform memory to the memory in the system - all memory is global
NUMA the processors have a local memory that is also part of shared global memory
COMA is NUMA with all the memory as a cache memory
NORMA is a multicomputer system. The processors do not have a global memory
Feature Multiprocessor Multicomputer
Structure Close coupledShare Bus and Clock Loosely coupledSeparate systems
Resource sharing Share all the resources
physically
Share the resources
logically
Inter Process Com Shared memory Message passing
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Problem 2.3
Part A and B
See Table 2.1 on page 76
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Problem 2.3
Graph and string reduction
Consider the expression E = (A + B) + (C + D)
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= +
E + +
A B C D
Write the string as
= (E, + ( + (A, B), + (C, D)))
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Problem 2.4
S1 S2 S3 S4
A = B + D C = A * 3 A = A + C E = A/2
Statement Inputs Outputs
S1 B, D A
S2 A, 3 C
S3 A, C A
S4 A, 2 E
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Problem 2.4
S1 S2 S4 S3
X = Sin (Y) Z = X + W X = Cos (Z) Y = -2.5 * W
Statement Inputs Outputs
S1 Y X
S2 X, W Z
S3 W, 2.5 Y
S4 Z X
S1 S2 || S3 S4
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Problem 2.4
For I = 1
A2 = B0 + C1 B1 = A1 * K C1 = B1 - 1
For I = 2
A3 = B1 + C2 B2 = A2 * K C2 = B2 - 1
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Problem 3.4
Speedup Sn = (W1 + Wn) / (W1 + Wn / N)
= Work done by one machine / Work done by all
= ( + (1 - )*K) / ( + (1 - ))
= K - C*(K-1)
For = 0 Sn = K
For = 1 Sn = 1
For calculating the mean = I do not know
Average will be the integral of the speedup equation from a to b divided
by the range (b-a)
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Problem 3.13
Problem for me. The concepts Ra, Rh, R1, R2
etc. are not known to me at this moment.
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Instruction pipeline
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Fetch Decode Execute Write
0 1 2 3 4 5 6 7
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Instruction pipeline
Instruction pipeline cycle
Instruction issue latency
Instruction issue rate
Instruction execution time
Base scalar machine
IIL = 1, IIR = 1, IET = 1
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Instruction pipeline
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Fetch Decode Execute Write
0 1 2 3 4 5 6 7 8
Resource conflicts will prevent issuing of instructions reducing pipeline
effect
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Instruction pipeline
Address PC
Data IR
ALU
Control Unit PSW
Register file
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Instructionssome definitions
Instruction codes
Memory references
Address modes
GPR General Purpose Registers HLL High Level Language
HLL Features in Instructions
Interrupts
ISR Interrupt Service Routine
Stack Pointer SP, Base Register BR
JSR Jump to Sub Routine
RTS Return from Subroutine
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Instructions
CISC Complex Instruction Set Computer
RISC Reduced Instruction Set Computer
Complex instructions take chip space andmay be used occasionally
Complex tasks done by series of simple
instructions
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Instructions
Simplify processor design
Simplify compiler design
Fixed instruction format
Simple addressing modes
Larger register sets
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Instructions
Hardwired
Microprogrammed
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CISC
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Control Unit Instruction and Data Path
Micro programmed
Control Memory
Cache
Main Memory
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RISC
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Hardware Control Unit Data Path
Instruction Cache Data Cache
Main Memory
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RISC Vs CISC
CISC Architecture RISC Architecture
Large set of instructions
variable formats
Small set of instructions
fixed format
Many Addressing Modes Limited Addressing Modes
Less number of GPRs Large number of GPRs
Larger and variableCycles Per Instruction Smaller and uniformCycles Per Instruction
Micro coded Instruction Set Hardware Instruction set
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VAX 8600 Architecture
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Main Memory
8 MB
I/O Subsystem
Memory and
I/O Control
TLB
Cache
16KB
Instruction
Unit
16 GPRs
Control
Memory
Floating
Point Unit
Execution
Unit ALU
ConsoleConsole Bus
Virtual Address Bus
GPR General Purpose Registers
TLB Translation Look aside Buffer
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MC68040 Microprocessor
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BusController
Address bus
32 bits
Data bus
32 bits
Bus control
signals
ATC Cache
MMU Controller
Instruction Memory Unit
MMU Controller
ATC Cache
Data Memory Unit
Floating
Point Unit
Instruction
Fetch
Integer Unit
Write back
Execute
EA
Calculation
Decode
EA Fetch
Execute
Write back
Convert
Data Bus
Instruction Bus
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RISC advantages
Simple instructions
Faster Instruction issue rate better pipeline effect
Uses lesser resources
Uses register files One memory operation at a time (Load or Store instructions)
Lesser and simpler addressing modes
Lesser chip density and area
Better Cycles Per Instruction
Simple instruction set helps optimizing compilers
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RISC disadvantages
Larger program size
Complex operations are performed by use of software functions
Good compiler support and standard function library required
Compiler must be a good optimizing compiler
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RISC compiler specialities
Concept of cooperating procedures
Concept of context frames
Stacking of context and nesting of frames
Sharing of registers in cooperating procedures In, Out, and Local registers of procedures and their sharing
Concept of context switching and stack operations
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