appendix b - reduction of digital logic

Appendix B - Reduction of Digital Logic

ion) of Boolean ns

anonical SOP (or POS) forms.

translates to a lower gate

uction, Karnaugh map ) reduction.

nction Circuit r the unreduced majority liminated, one AND gate has

as only two inputs instead of uced further? How do we go

B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction of Two-Level Expressions B.3 State Reduction

ca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring

function, the inverter for C has been ebeen eliminated, and one AND gate hthree inputs. Can the function by redabout it?

B-1 Appendix B - Reductio

Principles of Computer ArchitecMiles Murdocca and Vincent Heuring

Appendix B: Reduction of DigiLogic

Chapter Contents

n of Digital Logic

ca and V. Heuring

n of Digital Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring

Reduction (SimplificatExpressio

• It is usually possible to simplify the c

• A smaller Boolean equation generally count in the target circuit.

• We cover three methods: algebraic redreduction, and tabular (Quine-McCluskey

Reduced Majority Fu• Compared with the AND-OR circuit fo

enn Diagram jority Function

represents a minterm.

a Karnaugh Map.

y Function ds to that minterm.

ap around”

majority circuit, but this one is in its minimal two-level fo

ca and V. Heuring

• Cells on the outer edge of the map “wr

The Algebraic Method • Consider the majority function, F. We apply the algebrai

to reduce F to its minimal two-level form:

The Algebraic Method • This majority circuit is functionally equivalent to the prev

n of Digital Logic

ca and V. Heuring

c method

n of Digital Logic

Karnaugh Maps: VRepresentation of Ma

• Each distinct region in the “Universe”

• This diagram can be transformed into

K-Map for Majorit• Place a “1” in each cell that correspon

pings inimal (but logically

allest groups first.

gically Adjacent

• F = BC + AC + AB

• The K-map approach yields the same minimal two-level the algebraic approach.

ca and V. Heuring

form as

Adjacency Groupings for MajorFunction

• F = BC + AC + AB

Minimized AND-OR Majority Cir

n of Digital Logic

ca and V. Heuring

n of Digital Logic

K-Map Grou• Minimal grouping is on the left, non-m

equivalent) grouping is on the right.

• To obtain minimal grouping, create sm

K-Map Corners are Lo

on’t Cares

key) Reduction

AND followed by OR. Inverters are not included in the twcount). Algebraic reduction can result in multi-level circueven fewer logic gates and fewer inputs to the logic gate

ca and V. Heuring

o-level its with s.

• Tabular reduction begins by grouping minterms for which F is nonzero according to the number of 1’s in each minterm. Don’t cares are considered to be nonzero.

• The next step forms a consensus (the logical form of a cross product) between each pair of adjacent groups for all terms that differ in only one variable.

K-Maps and Don’t Cares • There can be more than one minimal grouping, as a res

cares.

3-Level Majority Circuit • K-Kap Reduction results in a reduced two-level circuit (t

n of Digital Logic

ca and V. Heuring

ult of don’t

n of Digital Logic

hat is,

Truth Table with D

• A truth table representation of a single function with don’t cares.

Tabular (Quine-McClus

of Choice ntial prime implicants and , producing the eligible set.

ruth Table into play for multiple hared among the functions.

function, although not necessarily minimally.

• A table of choice is used to obtain a minimal cover set.

functions, in which minterms can be s

On considère la fonction = 1 pourles mintermes

Implicantspremier

Mintermes

0000 0001 0011 0101 0110 0111 1010 1011

000‐ √ √

011‐ √ √

101‐ √ √

0‐‐1 √ √ √ √

‐‐11 √ √ √ ‐1‐1 √ √

Table of ChoiceOn élimine les don’t care

• The prime implicants form a set that completely covers the

n of Digital Logic

ca and V. Heuring

1101 1111

√ √

n of Digital Logic

Reduced Table • In a reduced table of choice, the esse

the minterms they cover are removed

• F = ABC + ABC + BD + AD

Multiple Output T• The power of tabular reduction comes

or a NOT Gate

osition

• The speed of a digital system is governed by:

• the propagation delay through the logic gates and • the propagation delay across interconnections. • We will look at characterizing the delay for a logic gate, a

method of reducing circuit depth using function decomposition.

ca and V. Heuring

Multiple Output Table of ChoiF0(A,B,C) = ABC + BC

F1(A,B,C) = AC + AC + BC

F2(A,B,C) = B

Speed and Performance

n of Digital Logic

ca and V. Heuring

n of Digital Logic

Propagation Delay f• (From Hamacher et. al. 1990)

MUX Decomp

g Tree

e Table

• Description of state machine M0 to be reduced.

• A reduced state table for machine M1.

OR-Gate Decomposition • Fanin affects circuit depth.

State Reduction

n of Digital Logic

ca and V. Heuring

n of Digital Logic

Distinguishin• A next state tree for M0.

Reduced Stat

educed State

te Assignment

Sequence Detector State TransitDiagram

Sequence Detector State Tab

n of Digital Logic

ca and V. Heuring

n of Digital Logic

Sequence Detector RTable

Sequence Detector Sta

ables st be applied at the inputs

ts at time t+1.

Sequence Detector

Circuit

Sequence Detector K-Maps • K-map

reduction of next state and output functions for sequence detector.

n of Digital Logic

ca and V. Heuring

n of Digital Logic

Excitation T• Each table shows the settings that mu

at time t in order to change the outpu

Serial Add

dder Circuit

te Machine

Serial Adder Next-State Functio• Truth table showing next-state functions for a serial add

R, T, and J-K flip-flops. Shaded functions are used in the

J-K Flip-Flop Serial Adder Circ

n of Digital Logic

ca and V. Heuring

ns er for D, S- example.

n of Digital Logic

D Flip-Flop Serial A

Majority Finite Sta

n of Digital Logic

ca and V. Heuring

n of Digital Logic

nt flip-

B-43 Appendix B - Reduction of Digital Logic

Majority FSM Circuit

flops; and (b) using T flip-flops.

ca and V. Heuring

Majority FSM State Table • (a) State table for majority FSM; (b) partitioning; (c) re

state table.

Majority FSM State Assignme• (a) State assignment for reduced majority FSM using D

appendix b - reduction of digital logic

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