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ALTIUM LIVE 2018:PRACTICAL HIGH-SPEED DESIGN CONSTRAINTS

Randy Clemmons CID+San Diego PCBOctober 5, 2018

Technology Boom Cycle

Virtual RealityArtificial IntelligenceInternet of ThingsDronesDriverless CarsRoboticsHyperloopBig DataMedical Devices

What do they have in common ?Highspeed data processing ?

Practical High Speed Design Constraints

Transition Propagation Delay (Tpd) and Velocity of electromagnetic fields in circuit boards.

Should high-speed designers consider the propagation delay of signals ?

Velocity of electromagnetic waves in a typical circuit boards is approximately 60% the speed of light.

Electromagnetic waves travel through dielectric materials guided by copper features in the signal and return paths.

Propagation Delay is the Reciprocal of Velocity

Where: Er = Effective Er (Dk) = Keffc = Speed of light (300,000,00 m/s) 186,000miles/hourVp = VelocityTpd = Transistion Propagation Delay

Source: https://en.wikipedia.org/wiki/Transmission_line

For FR4 materials the dielectric constant known as Eror Dk can vary greatly from ~3.8 to 4.7. And the Dk number in the datasheet for the material is the neat resin number. The neat resin number is the epoxy only Dk, before factoring in the fiberglass woven material.

1080 2116 7628

370HR Dk ~ 4 (Resin Only)E-Glass Dk ~ 6

1080 2116 7628

Fabricators rarely provide the effective dielectric constant.

Typical Propagation Delay (Tpd)

Signals travel faster on outer layersTpd expressed in Pico Seconds per inch.

Equations for Tpd, Keff, Co, Lo, Zo

Using Saturn PCB Design Toolkit to find Keff and Tpd

Effective Dielecric (Keff) = Air + Soldermask + Dielectric

Using Saturn PCB Design Toolkit to find Tpd for Stripline

Stripline is approximately 20pSec per inch slower than MicrostripEffective Er (Keff) approximately equals Dk in Stripline.

1GBIT DDR2 SDRAM – Top Layer Routing

Simple Example Design

Layer 1 SIG Layer 2 GND

Layer 3 SIG Layer 4 VREF

Vias NOT included in Length Matching (copper track length)

Before xSignals and Net length data which includes vias

Vias included in Length Matching (copper track length)

After xSignals and Net length data which includes vias

Vias included in Length Matching (Flight Time pSec/inch)

Flight Time Calculated using Tpd per inch

Chuy’s Trailer Park Calafia (Rosarito) Mexico – Winter 1998

Timing is Critical !

Critical trace length for a signal with 1nS Risetime is ~ 1.5 inches

Enter Er Eff, Risetime as the PeriodSet Wavelength Divide to 1/4

Critical 50 Ohm path ?

Path length 486mils

Length of Vias defined by the Stackup

Enter dielectric thickness before length matching

Clean Tracks ! (No Net Antennas or Extra bits of Copper

90 Degree Corners

Designers have been lead to believe that routes with square corners are a bad thing and they assume all square corners should be eliminated from a design.

I have some bad news for the no square corners camp. Every surface mount resistor placed on the board will introduce four sharp 90 degree turns in the signal path. I suggest they figure out how to design their boards without using resistors :)

Source: Altium Bloghttps://resources.altium.com/pcb-design-blog/pcb-routing-angle-myths-45-degree-angle-versus-90-degree-angle

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ALTIUM LIVE 2018:PRACTICAL HIGH-SPEED DESIGN CONSTRAINTS

Randy Clemmons CID+San Diego PCBOctober 5, 2018

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