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Unit 3: Reading Data3-1PrimeTime: Introduction to Static Timing Analysis
3-1
Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Agenda: Day One
DAY1 Register to Register Paths LabUnit Register to Register Paths LabUnit
Reading Data3
Constraining Internal Reg-Reg paths4
Writing Basic Tcl Constructs in PT 2
Introduction to Static Timing Analysis1
Welcome0i
Unit 3: Reading Data3-2PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Unit Objectives
After completing this unit, you should be able to:
� Use a 3 step flow to read design(s) into PT memory
� Resolve errors and warnings associated with readingand linking a design
� Access design objects after a design has been readinto PT memory
Unit 3: Reading Data3-3PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Reports
PrimeTime
Technology Libraries
Gate-LevelNetlist Constraints Exceptions
SetupFile
ConstraintScript
LogFile
read_dbread_verilog
read_vhdl
source source
Read at PTinvocation
Loaded at linking
The Inputs and Outputs of PrimeTime
The PrimeTime setup file is .synopsys_pt.setup.Constraints and Exceptions are usually placed in “script(s)”.
Unit 3: Reading Data3-4PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Five Step Static Timing Analysis Flow
READREAD
CONSTRAINCONSTRAIN
EXCEPTIONSEXCEPTIONS
CHECKCHECK
ANALYZEANALYZE
Our Focus
Unit 3: Reading Data3-5PrimeTime: Introduction to Static Timing Analysis
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PRIMETIME Interfaces
Two ways to interface to PrimeTime (PT)
PT GUI
pt_shell
PRIMETIME(PT)
Engine
Command line shell
primetime
Primetime only accepts Tcl mode.
Unit 3: Reading Data3-6PrimeTime: Introduction to Static Timing Analysis
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Three Steps to Read Your Data into PT
Three steps to read in the required design(s):� Set Variables:
� search_path
� link_path
� Read Design
� Resolve References (Link design)
Unit 3: Reading Data3-7PrimeTime: Introduction to Static Timing Analysis
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1: Set the search_path Variable
ProjectX/
tech_lib.db
projectX.log
db/ vlog/ scripts/blockA.db
blockB.db
blockC.db
top.v
blockD.v
blockE.v
top.pt
proc1.pt
proc2.pt
Tom/uart.db
set search_path ”$search_path db vlog scripts”
printvar search_path
Synonymous with UNIX path variable
What is a search_path?search_path contains a list of paths used to locate the designs, libraries and other files needed toperform STA.
search_path variable usually includes paths to:Design Database(s)Timing Model(s)Technology LibraryConstraint files
These two commands have the same effect:set search_path “$search_path db vlog scripts”.# lappend search_path “db vlog scripts”lappend search_path db vlog scripts
The default value of search_path is empty string “”.
Unit 3: Reading Data3-8PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
1: Set the link_path variable
� The Link Path specifies where PT searches for designs andlibrary files when linking the design:
set link_path {* tech_lib.db rams.db}
PT Memory“*”
TechnologyLibrary
CustomConditions
IPCores
LinkPath = + + +
� During linking, PT will search (in sequence) the:� PT Memory (*)� Library file tech_lib.db� IP core rams.db
printvar link_path
link_library = link_path.Design Compiler uses link_library, PrimeTime uses link_path.
These two commands are equivalent:set link_path {* core_slow.db rams.db}lappend link_path core_slow.db rams.db
Unit 3: Reading Data3-9PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
pt_shell> read_db top.db
pt_shell> read_db blockA.db
pt_shell> read_db blockB.db
OR
pt_shell> read_db “blockA.db blockB.db top.db”
blockA
top
INVU21
U33
U4
blockB
What is the current_design in each case?
2: Manually Read Design(s) into PT
The last design read is the current design by default. You can make another design current with thecurrent_design command.
In the above example of 2 cases, the current designs are blockB and top respectively.
Unit 3: Reading Data3-10PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
2: Read Sub Designs Automatically
pt_shell> read_verilog top.v
pt_shell> link_design TOP
ProjectX/
tech_lib.db
projectX.log
db/ vlog/ scripts/blockA.db
blockB.db
blockC.db
top.v
blockD.v
blockE.v
top.pt
proc1.pt
proc2.pt
Tom/uart.db
What should the search_path be?
Top.v is in the vlog directory, search_path should have this directory.Designs blockA.db AND blockB.db are in the DB directory; search_path should also have thisdirectory.
set search_path “./vlog ./db”
Unit 3: Reading Data3-11PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
2: Read Designs in Different Formats
pt_shell> read_verilog top.v
pt_shell> read_db blockA.db
pt_shell> read_vhd blockB.vhd
blockA
top
INV
U21
U33
U4
blockB
Can you mix netlist formats? How does it work?
Unit 3: Reading Data3-12PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Example 1: Read Problem
pt_shell> read_db uart.db
Error: Cannot read file ‘uart.db’
Error: Problem in read_db: No designs were read.
set search_path ”$search_path db vlog scripts”set link_path “* tech_lib.db”
How would you fix this read problem?
ProjectX/
tech_lib.db
projectX.log
db/ vlog/ scripts/blockA.db
blockB.db
blockC.db
top.v
blockD.v
blockE.v
top.pt
proc1.pt
proc2.pt
Tom/uart.db
Error !
Unit 3: Reading Data3-13PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Example 2: Read Problem
pt_shell> pwd
/…../ISTA/ProjectX
pt_shell> cd scripts
pt_shell> read_db blockA.db
Error: Cannot read file ‘blockA.db’
set search_path ”$search_path db vlog scripts”set link_path “* tech_lib.db”
How would you fix this read problem?
ProjectX/
tech_lib.db
projectX.log
db/ vlog/ scripts/blockA.db
blockB.db
blockC.db
top.v
blockD.v
blockE.v
top.pt
proc1.pt
proc2.pt
Tom/uart.db
Error !
Unit 3: Reading Data3-14PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
BLOCKB
BLOCKA
RISC_CORE
INV
Where is BLOCKB? What is INV?
How will PrimeTime know what each instance in RISC_CORE design netlist refers to?
U21
U33
U4
3: What is Resolving References?
Resolving references (aka link) means finding and replacing the space holders with the actual librarycells or sub designs referenced.
Unit 3: Reading Data3-15PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
3: Link the Design to Resolve References
The link_design command:
� Resolves all references in a design using the link_path variable:� If it fails, it will use the search_path variable to resolve references
� Reads the technology library if not already read in
blockA
top
INV
U21
U33
U4
blockB
What are blockA,blockB, and INV?
link = link_design.Design Compiler (DC) uses link while PrimeTime (PT) uses link_design command to link adesign.For convenience, PT has built-in alias link for link_design.
Q: What happens if you accidentally try to link the same design that has been previously linked?A: If you originally used “-remove_sub_designs” then, black boxes will be resulted since sub design references could not be found in the memory (*).Solution: - Use the link -incr option (OR) - Remove the (corrupted) design in memory and start over from read again (Recommended).
Unit 3: Reading Data3-16PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Example: Linking a Design
pt_shell> read_db “blockA.db blockB.db”
pt_shell> read_verilog top.v
pt_shell> current_design top
pt_shell> link_design
blockA
top
INVU21
U33
U4
blockB
set search_path ”$search_path db vlog scripts”set link_path “* tech_lib.db”
Where are the references found during linking?
ProjectX/
tech_lib.db
projectX.log
db/ vlog/ scripts/blockA.db
blockB.db
blockC.db
top.v
blockD.v
blockE.v
top.pt
proc1.pt
proc2.pt
Tom/uart.db
PT found blockA.db and blockB.db in its memory and INV in the library.After linking, if current_design is set to a different design, all the previously established linkinformation will be gone.
PT automatically reads in Library file(s) when link_design is executed.
Unit 3: Reading Data3-17PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Example: Link Warning
pt_shell> linkLinking design CLOCK_GEN...Warning: Unable to resolve reference to 'MUX21L' in 'CLOCK_GEN'. (LNK-005)Warning: Unable to resolve reference to 'IVI' in 'CLOCK_GEN'. (LNK-005)Warning: Unable to resolve reference to 'FD2' in 'CLOCK_GEN'. (LNK-005)Creating black box for U31/MUX21L...Creating black box for U32/MUX21L...Creating black box for U34/IVI...Creating black box for U35/IVI...Creating black box for CLK_BY_2_reg/FD2...
Designs used to link CLOCK_GEN: <None>
Libraries used to link CLOCK_GEN: <None>
Design 'CLOCK_GEN' was successfully linked.1
pt_shell> read_db CLOCK_GEN.dbpt_shell> link_design
Linking design CLOCK_GEN...Warning: Unable to resolve reference to 'MUX21L' in 'CLOCK_GEN'. (LNK-005)Warning: Unable to resolve reference to 'IVI' in 'CLOCK_GEN'. (LNK-005)Warning: Unable to resolve reference to 'FD2' in 'CLOCK_GEN'. (LNK-005)Creating black box for U31/MUX21L...Creating black box for U32/MUX21L...Creating black box for U34/IVI...Creating black box for U35/IVI...Creating black box for CLK_BY_2_reg/FD2...
Designs used to link CLOCK_GEN: <None>
Libraries used to link CLOCK_GEN: <None>
Design 'CLOCK_GEN' was successfully linked.1
Verify link_path and search_path
WHAT!
Primetime create black boxes for unresolved references.This is because the link_create_black_boxes variable is set to true by default.
Unit 3: Reading Data3-18PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Black Boxes with link_design
If link_design could not resolve a particular reference,PT will create black boxesA black box is an empty cell with no timing arcs
� The variable link_create_black_boxes is true by default:� Substitute unresolved references with black boxes� Design is linked and timing analysis can be performed
� Set the variable link_create_black_boxes to false:� Unresolved references, cause a design to remain unlinked� Most timing analysis commands will not function� Fix any problems and re-link the design
What command would you use to set this variable to false?
set link_create_black_boxes false
Unit 3: Reading Data3-19PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Test For Understanding
� Name three design netlist formats that PrimeTimeaccept?
� ___� ___� ___
� Linking a design involves the use of:a) _________________ and b) _________________ variables
� What is the purpose of linking a design?____________________________________________
� What does “*” in the link_path mean?____________________________________________
Unit 3: Reading Data3-20PrimeTime: Introduction to Static Timing Analysis
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Do You need to Set Variables Every Time?
Can you have search_path and link_path variables
set automatically when you invoke PT?
Unit 3: Reading Data3-21PrimeTime: Introduction to Static Timing Analysis
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Create a .synopsys_pt.setup File
set search_path ”$search_path db vlog scripts”set link_path “* tech_lib.db”
set sh_enable_page_mode trueset sh_command_log_file projectX.log
alias h historyalias rc “report_constraint -all_violators”history keep 200
Within the setup file, you can:� Create commands you want to execute every time PrimeTime is
invoked, i.e. “set search_path or set link_path”
� Define aliases for interactive use
� Change log file name from its default pt_shell_command.log
history keep 200 specifies:the number of commands (200) to be retained in the history list. By default, only 20 commands areretained.
You can control the naming of the Log file (default: pt_shell_command.log) via the variable:sh_command_log_file, but, it should appear inside the setup file (.synopsys_pt.setup)Example: set sh_command_log_file ./projectX.log.
Do not source any script file in the setup file since it will increase invocation time and will makedebugging difficult.
Unit 3: Reading Data3-22PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
PrimeTime Setup Files
./.synopsys_pt.setup
~/.synopsys_pt.setup .synopsys_pt.setup
$SYNOPSYS/admin/setup~user
Project_Directory
User’s Specific Project Setup
User’s GeneralSetup
StandardSetup
13
2
PrimeTime will read the .synopsys_pt.setup files from three directories (in the following order):
1. The “primetime root” directory, which contains the PrimeTime files. For example, if PrimeTimewas installed under /tools/synopsys/PT, standard installation would include a setup file under/tools/synopsys/PT/admin/setup.
2. Once the “standard” setup file has been read in and executed, PrimeTime then searches for a setupfile in the user’s login directory. If a setup file exists in this directory, it will be read in andexecuted.
-- Warning: During project archiving (using tar -cvf) you need to think about it!
3. Last, PrimeTime will read in and execute the .synopsys_pt.setup file from the directory underwhich it was invoked.
-- It makes life easier if this project specific setup file contains everything including the contents ofyour home directory setup file, if you have one -- recall the Warning above.
Unit 3: Reading Data3-23PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
Read/Link Problem Debug Check List
� Is PT invoked in the correct directory? Correct setup file?
� Is the design fully mapped to gate level instances?� No high level HDL constructs (such as if, case,...)
� Are search_path and link_path variables set correctly?� printvar *_path
� Are Black Boxes created for unresolved references?� set link_create_black_boxes false
� Check Libraries in Memory & Library used:� list_libraries� list_libraries -used
There can be only one linked design in PT memory
Q: What happens if you accidentally try to link the same design that has been previously linked?A: If you originally used “-remove_sub_designs” , the result will be black boxes since sub design
references could not be found in the memory (*).Solution: - Use the link -incr option (OR) - Remove the (corrupted) design in memory and start over from read again (Recommended).
Unit 3: Reading Data3-24PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
How does PT Store My Design Netlist?
D0 Q[1:0]
D1
REGFILE
U4
OUT[1:0]INV0
INV1
AIN
BIN
CIN
DIN
Q0
Q1
ENCODER
INV
INV
U1U2
A
B
C
D
CLK
BUS0
BUS1
A
B
C
D
CLK
U3
TOP
Pin
CLKClock
Reference and Design
Design Cell Net
Port
Vocabulary of Design Objects
Here are some commands to access your design stored in PT memory:
get_cells # Create a collection of cells
get_clocks # Create a collection of clocks
get_nets # Create a collection of nets
get_pins # Create a collection of pins
...
all_clocks # Create a collection of all clocks in design
all_inputs # Create a collection of all input ports in design
all_outputs # Create a collection of all output ports in design
all_registers # Create a collection of register cells or pins
…..
Unit 3: Reading Data3-25PrimeTime: Introduction to Static Timing Analysis
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Reading DataPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16
list_librariesreport_lib LIB_NAME
What Information Is Found in the Library?
� Units for time, capacitance, resistance
� List of library cells
� Cell Timing (propagation delay, setup, hold ...)
� Operating conditions
� Wire load model
� Design rules (max_capacitance, max_fanout ...)
pt_shell> list_librariesLibrary Registry: * ssc_core_slow …./core_slow.db::ssc_core_slowpt_shell> report_lib ssc_core_slow****************************************Report : libraryLibrary: ssc_core_slowVersion: 2002.03****************************************
Time Unit : 1 nsCapacitance Unit : 1 pF
Usually, library file is read in during link_design. You can also explicitly read in a library file usingthe read_db command:Example: read_db ssc_core_slow.db
To remove all the designs and libraries from the memory:remove_design –allremove_lib –all
NOTE: PT cannot remove a library if it is used by a design residing in memory.
Unit 3: Reading Data3-26PrimeTime: Introduction to Static Timing Analysis
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Lab Overview
LAB
45 min
� Given a set of design and library files, you willneed to successfully read them into PrimeTimememory and access the design objects
� You will set the search_path and link_pathvariables correctly such that you can read:� A Top level Verilog/VHDL netlist and link using
Verilog/VHDL sub blocks and the library� A top level Verilog/VHDL netlist and link using DB sub
blocks and the library� A complete netlist in VHDL/Verilog/DB and library, link
efficiently and access sevaral objects within the design
Unit 3: Reading Data3-27PrimeTime: Introduction to Static Timing Analysis
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Review
� Write 3 variable names that are used to read and link adesign in PT:
________________________________________________
________________________________________________
________________________________________________
� Write 3 command names that are used to read and link adesign in Verilog format into PT:
________________________________________________
________________________________________________
________________________________________________
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