a 0.15 m radiation-hardened antifuse field programmable gate array technology
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MAPLD 2005 / E134Rockett
A 0.15M Radiation-Hardened Antifuse Field Programmable Gate Array Technology
The RH AX250-S production installation effort is sponsored by the Defense Threat Reduction
Agency.
Leonard Rockett1, Dinu Patel1, Steven Danziger1, Balwinder Sujlana1, Les Palkuti2, John McCollum3, J.J. Wang3,
Brian Cronquist3, Farid Issaq3 and Frank Hawley3
1BAE SYSTEMS, 9300 Wellington Road, Manassas, VA 20110-41222Defense Threat Reduction Agency, 6801 Telegraph Rd, Alexandria VA 22310
3Actel Corporation, 2061 Stierlin Ct, Mountain View, CA 94043
MAPLD 2005 / E134Rockett
MAPLD 2005 / E134Rockett
Outline
• Introduction
•Process Development
– Base Radiation Hardened Process –Anti-fuse –High Voltage Transistor
•Radiation Results
–Total Ionizing Dose–Single Event Gate Rupture–Single Event Upset
•Summary
1
MAPLD 2005 / E134Rockett
Introduction
• FPGA products are used extensively in space systems- Since 1996, BAE Systems has supplied Actel over 25,000 ONO anti-fuse based Rad Hard FPGA’s
• Next generation radiation hardened Metal to Metal (M2M) anti-fuse based FPGA is needed for advanced military and space applications
• Actel and BAE SYSTEMS are developing next generation RH FPGA, leveraging:
- Our decade long collaboration- Actel’s proven rad tolerant FPGA design - BAE Systems’ newly modernized rad hard CMOS technology capabilities.
2
MAPLD 2005 / E134Rockett
RH15Radiation Hardened
Base Process
Radiation Hardened FPGA – AX250-S
FPGAUnique features-High Voltage Tx
- Anti-fuse
RHAX250-S Approach
Final stages
3
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Off-Current Total Ionizing Dose Response for 3.3V NFET Transistor
High voltage NFET transistors exceed hardness requirements
Unhardened Sample
Hardened Splits
4
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Total Dose Response for Parasitic Isolation (STI) Device
High voltage transistor isolation exceeds hardness requirements
Unhardened Sample
Hardened Splits
5
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– Gamma-Cell• Dose-rate = 46rd(SiO2)/s
• Maximum Dose = 2Mrd(SiO2)
• Room temperature• Known pattern (all 1’s)
clocked into circuit• Vdd(Core) = 1.65V• Vdd(I/O) = 3.6V
TID Radiation Testing - RH15 High Speed CktRH15 Base process
PDV3 Chiplet-1 Idd(Q) Core-Current versus Gamma-Dose [Vcore=Vdd+10%]
0
1
2
3
4
5
6
7
8
10 100 1000 10000
Gamma-Dose krd(SiO2)
Idd
(Q)
[Co
re-C
urr
en
t] (
mA
)Avg (5-Modules)
Chip 657D-5 C
pre-rd
Error-bars are minimum and maximum of dataset
6
DC parametric shows stability to 2Mrd(SiO2)
Idd(Q)-Core shows very little change in value after 2Mrd(SiO2)
MAPLD 2005 / E134Rockett
TID Radiation Testing on High Speed CktRH15 Base process
RH15 High Speed Circuit shows >1GHz performance both pre- and post-irradiation (2 Mrd(SiO2))
RH15 High Speed Circuit shows >1GHz performance both pre- and post-irradiation (2 Mrd(SiO2))
PDV3 Chiplet-1 Operation-Frequency versus Gamma-Dose [Vcore=Vdd+10%]
0
2000
4000
6000
8000
10000
12000
14000
10 100 1000 10000
Gamma-Dose krd(SiO2)
Op
era
tio
n F
req
ue
nc
y (
MH
z)
Avg (5-Modules)
Chip 657D-6 C
pre-rd
Error-bars are minimum and maximum of dataset
7
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TID Testing on 4Mb SRAM RH15 Base process
PDV3 150nm Millennium 4Mb SRAM: Idd(Q-core)Inv-Dose-Pattern
0
5
10
15
20
25
30
35
40
10 100 1000 10000
Gamma-Dose (krd(SiO2))
Idd
(Q-c
ore
) In
v-D
os
e-P
att
ern
(m
A)
1667
1668
1670
1671
1666-C
pre-rd
PDV3 150nm Millennium 4Mb SRAM: Write-Pulse Width
1
1.5
2
2.5
3
3.5
4
10 100 1000 10000
Gamma-Dose (krd(SiO2))
Wri
te-P
uls
e W
idth
(n
s)
1667
1668
1670
1671
1666-C
pre-rd
PDV3 150nm Millennium 4Mb SRAM: Access-Time
8
8.5
9
9.5
10
10.5
11
10 100 1000 10000
Gamma-Dose (krd(SiO2))
Ac
ce
ss
-Tim
e (
ns
)
1667
1668
1670
1671
1666-C
pre-rd
8
DC & AC parameters and functionality show very little change after 2Mrd(SiO2)
MAPLD 2005 / E134Rockett
RH15Radiation Hardened
Base Process
Radiation Hardened FPGA – AX250-S
FPGAUnique features-High Voltage Tx
- Anti-fuse
RHAX250-S Approach
Final stages
9
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RTAX250-S
RHAX250-S
Process & Design Rule Development
Process Integration / Technology Validation
Product Demonstration
• RTAX250-S design transferred to BAE
QML Qualification
Actel-BAE collaboration supported by DTRA
RHAX250-S Product Road Map
Completing
First FPGA lots started
10
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Radiation Hardness Features
Total Ionizing Dose: 1Mrad (Si)Single Event Latchup: ImmuneSingle Event UpsetLET: > 37MeV-cm2/mgSETe-RAM: < 1E-10 e/b-d (EDAC)TMR-hardened registers.
RHAX250-S Product Features:M2M Antifuse Structure:
RHAX250-S FPGA Product
M2M antifuse
Metal 6
Metal 7
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SEM Cross-section of Metal to Metal Anti-fuse
Ti
TEOS
TiN
TiN
Amorphous Si
W- Stud
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Anti-Fuse Time Dependent Dielectric breakdown
Anti-fuse element TDDB meets or exceeds requirements
TDDB of BAE @ Vot@rmt [Lot 2040643 W#20]
-5
-4-3
-2
-1
01
2
34
5
6
78
9
10
1112
13
1415
16
17
1819
20
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38
1/v
LINEST WAF#201ms=0.131
Log T ime=284.5(1/ v)-40.26
15
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PFET High Voltage Transistors Data
High voltage PFET process optimization is very encouraging
RHFPGA Pfet VtBB vs Process SplitVsub = 6v
-2.5
-2
-1.5
-1
-0.5
0
1 2 3
Split
VtB
B (
v)
649_0.38um 649_0.40um 684_0.38um 684_0.40um LSL
RHFPGA Pfet BVJ vs Process Split
-10
-8
-6
-4
-2
0
1 2 3
Split
BV
J (v
)
649_0.38um 649_0.40um 684_0.38um 684_0.40um USL
RHFPGA Pfet BVD vs Process Split
-10
-8
-6
-4
-2
0
1 2 3
Split
BVD
(v)
649_0.38um 649_0.40um 684_0.38um 684_0.40um USL
16
MAPLD 2005 / E134Rockett
NFET High Voltage Transistor Data
High voltage NFET optimization meets the specifications requirement
RHFPGA Nfet BVD vs Process Split
0
2
4
6
8
10
1 2 3 4 5 6 7 8
Split
BVD
(v)
649_0.38um 649_0.40um 684_0.38um 649_0.40um LSL
RHFPGA Nfet BVJ vs Process Split
0
4
8
12
1 2 3 4 5 6 7 8
Split
BV
J (v
)
649_0.38um 649_0.40um 684_0.38um 684_0.40um LSL
RHFPGA Nfet VtBB vs Process SplitVsub = 6v
0
0.5
1
1.5
2
1 2 3 4 5 6 7 8
Split
VtB
B (
v)
649_0.38um 649_0.40um 684_0.38um 684_0.40um USL
17
MAPLD 2005 / E134Rockett
SEDR Testing - Actel’s Prototype RTAX250
• Plotting power supply current (ICC) versus run time and checking ICC, there was no occurrence of SEDR in any test run. The maximum LET used at BNL was 60 MeV•cm2/mg, and the maximum LET used at TAMU was 54 MeV•cm2/mg.• Normal incidence is worst case for SEDR, so the worst case testing was performed in test runs with high LET ions.
0.0065
0.0066
0.0067
0.0068
0.0069
0.007
0.0071
0.0072
0.0073
0.0074
0.0075
0 50 100 150 200 250 300 350 400 450
Time (sec)
ICC
A (
A) ICCA has small fluctuations but
no significant permanent jumps, which would be the signature of SEDR.
18
MAPLD 2005 / E134Rockett
G
A
B
C
A
B
C
A
B
C
D
B
A
C
Q
Triple Modular Redundant Flip-Flop (K-Latch)
Triple Modular Redundant (TMR) Latch used for SEU Hardness19
MAPLD 2005 / E134Rockett
Hard-wired TMR Flip-Flop Cross-section per bit
Logic with TMR latches exceed hardness requirements
SER = 1.96x10-11 upsets/bit•day
1E-11
1E-10
1E-09
1E-08
0 10 20 30 40 50 60 70 80 90
LET (MeV-cm2/mg)
Cro
ss
Se
cti
on
(c
m2 )
Weibull Fit
20
MAPLD 2005 / E134Rockett
Summary
• BAE Systems and Actel Corporation continue their long successful collaboration – 0.15m radiation-hardened 250K gate FPGA for space in
development– Same form, fit, and function as commercial RT version
• RH process Total ionizing dose data meets target • Single Event Upset test results of TMR-hardened
flip-flop designs meet target, no occurrence of
SEDR observed during heavy ion testing• Full suite of radiation testing planned for Radiation Hardened
product demonstration
21
Product installation efforts are progressing well toward completion in early 2006, with qualified parts available in late 2006 The RH AX250-S production installation effort is sponsored by the Defense Threat Reduction Agency.
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