3 logical effort module

Logical Effort ModuleLogical Effort Module

VLSI System Design

Massoud PedramSpring 2008

Dept. of Electrical EngineeringUniversity of Southern CaliforniaUniversity of Southern California

Method of Logical EffortMethod of Logical Effort

• Easy way to estimate delay in a CMOS circuitEasy way to estimate delay in a CMOS circuit• Specifies the optimal number of logic stages on a path

to minimize its delayy• Estimates the best sizes for logic gates• Ideal for evaluating alternatives in the early stages ofIdeal for evaluating alternatives in the early stages of

a design• Provides a good starting point for more intricate ov des good s g po o o e c e

optimizations

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Integrated Circuit (IC) Design g ( ) g

• Chip designers face aChip designers face a bewildering array of choices:– What is the best circuit

topology for a function?H t f po

– How many stages of logic to get the least delay?

– How wide should the transistors be in each stage?

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stage?

3IC Design Flow

RC Delay ModelRC Delay Model

• Use equivalent circuits for MOS transistors– Ideal switch + capacitance and ON resistance– Unit nMOS has resistance R, capacitance C– Unit pMOS has resistance 2R capacitance C– Unit pMOS has resistance 2R, capacitance C

• Capacitance is proportional to width• Resistance is inversely proportional to widthy p p

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Assumptions and NotationAssumptions and Notation

• Capacitance– C = Cg = Cs = Cd

• ResistanceP ll U R i t P ll D R i t R– Pull-Up Resistance = Pull-Down Resistance = R

• Unit transistors – May refer to minimum contacted device (4/2 λ)– Doesn’t matter as long as you are consistent

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Inverter Delay EstimateInverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

Cd = 6RC

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Example: 2-input NANDExample: 2 input NAND

• Estimate rising and falling propagation delays of a 2-input g g p p g y pNAND driving h identical gates

22 Y6C

h copies2B h copies

(6+4h)CY ( )6 4pLHt h RC= +

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Example: 2-input NANDExample: 2 input NAND

• Estimate rising and falling propagation delays of a 2-input g g p p g y pNAND driving h identical gates

22 Y6C

h copies2B h copies

R/2 ( )( ) ( ) ( )2 6 4R R Rt C h C⎡ ⎤⎣ ⎦ +(6+4h)C2CR/2

R/2x Y ( )( ) ( ) ( )( )

2 2 22 6 4

pHLR R Rt C h C

= + +⎡ ⎤⎣ ⎦

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Delay ComponentsDelay Components

• Delay has two components:Delay has two components:– Parasitic delay

• 6 or 7 RC• Independent of the load

– Effort delay• 4h RC• 4h RC• Proportional to the load capacitance

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Logical Effort Technique Provides a Delay dUpper Bound

• Best-case delay can be substantially less than the propagation y y p p gdelay e.g., if both inputs fall simultaneously

(6+4h)CYR

( )3 2Best Caset h RC− = +

• Good layout minimizes the diffusion areaGood layout minimizes the diffusion area

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Gate Delay Modely

• General delay model for a gatey g

( )abs out pd kR C C= +

u dR R R= =

• Express delays in a process-independent unit

absddτ

=τ = 3RC

≈ 40 ps in 0.6 μm process

12 i 0 18

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12 ps in 0.18 μm process

Delay in a Logic Gatey g

• Delay has two components: d f p= +Delay has two components:– f : stage effort (a.k.a. effort delay)

• Again has two components i.e., f = g h

d f p+

– g: logical effort• Measures relative ability of gate to deliver current• g ≡ 1 for inverterg ≡ 1 for inverter

– h: electrical effort = Cout / Cin• Ratio of the output to input pin capacitance

– p: parasitic delay• It represents delay of a gate driving no load

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Delay PlotsDelay Plots

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d = g h + p13

Computing the Logical EffortComputing the Logical Effort

• Logical effort is the ratio of the input capacitance of a gate to g p p gthe input capacitance of an inverter delivering the same output current (related to resistance)

Calculate from delay vs fanout plots or– Calculate from delay vs. fanout plots or– Estimate from transistor width considerations

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Logical Effort (Cont’d)Logical Effort (Cont d)

• Alternatively logical effort of a gate is:y g g

,gate in gate

f l f l

• Most of the time, the reference template gate is a unit size i t b t th ti ll it b t

_ _ , _ _reference template gate in reference template gateR C

inverter, but theoretically it can be any gate

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Logical Effort of Common Logic GatesLogical Effort of Common Logic Gates

Gate type Number of inputs1 2 3 4 n

Inverter 1NAND 4/3 5/3 6/3 (n+2)/3NOR 5/3 7/3 9/3 (2n+1)/3Tristate Buffer / Mux

2 2 2 2 2MuxXOR, XNOR per bundle

4 12 32 n2n-1

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Logical Effort of Transmission Gateg

• Calculate the logical effort of a transmission gateCalculate the logical effort of a transmission gate

in out

PMOS:4R

PMOS:2R

NMOS:RFalling Transition:Effective resistance = 4/5R

NMOS:2RRising Transition:Effective resistance = R

LE d LE s= =

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Logical Effort for unequal rise/fall delaysLogical Effort for unequal rise/fall delays

• Gates with different pull-up and pull-downGates with different pull up and pull down resistances have different rising and falling logical efforts

• Calculate rising and falling logical effort for an inverter with 1PMOS NMOSW W= =

rising43

falling

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Effect of Sizing on the Logical EffortEffect of Sizing on the Logical Effort

• Sizing does not change the logical effort of a gateSizing does not change the logical effort of a gate– Let the size of a gate be increased by a factor α, then we

have: R C RCα

which proves that the logical effort is independent of gate sizing

C RCαα

sizing

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Parasitic DelayParasitic Delay

• Parasitic delay is set by ratio of the diffusionParasitic delay is set by ratio of the diffusion capacitance at the output node of the logic gate to the input capacitance of the reference template gate

,gate diff gate

f t l t t i f t l t t

_ _ , _ _reference template gate in reference template gateR C

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Parasitic Delay of Common Logic Gatesy g

• Parasitic delay given in multiples of pi (≈1)

Gate type Number of inputs

Parasitic delay given in multiples of pinv (≈1)

1 2 3 4 nInverter 1NAND 2 3 4 nNOR 2 3 4 nTristate Buffer / Mux

2 4 6 8 2n

XOR XNOR 4 6 8 2n

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XOR, XNOR 4 6 8 2n

Example: Ring Oscillatorp g

• Estimate the frequency of an N-stage ring oscillatorEstimate the frequency of an N stage ring oscillator

Logical Effort: g = 1 31 stage ring oscillator inLogical Effort: g = 1Electrical Effort: h = 1P iti D l 1

31 stage ring oscillator in 0.6 mm process has frequency of ~ 200 MHz

Parasitic Delay: p = 1Stage Delay: d = 2F f 1/(2*N*d) 1/(4N)

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Frequency: fosc = 1/(2*N*d) = 1/(4N)

Example: FO4 Inverterp

• Estimate the delay of a fanout-of-4 (FO4) inverterEstimate the delay of a fanout of 4 (FO4) inverterd The FO4 delay is about

200 ps in 0.6 μm process

60 ps in a 0.18 μm process

q / 3 ns in a q μm process

Logical Effort: g = 1El t i l Eff t h 4Electrical Effort: h = 4Parasitic Delay: p = 1St D l d 5

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Stage Delay: d = 5 ** remember this result

Multistage Logic NetworksMultistage Logic Networks

• Logical effort generalizes to multistage networks:Logical effort generalizes to multistage networks:– Path Logical Effort: i

G g= ∏

– Path Electrical Effort: out-path

in-path

– Path Effort: i i ii i

F f g h= =∏ ∏

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Paths that BranchPaths that Branch

• Can we write F = GH?Can we write F GH?– No! Consider paths that branch

G = 1G 1H = 90 / 5 = 18GH = 18 ?GH 18 ?h1 = (15 +15) / 5 = 6h = 90 / 15 = 6h2 = 90 / 15 = 6F = g1g2h1h2 = 36 = 2GH !

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Branching EffortBranching Effort

• Introduce the branching effortIntroduce the branching effort– Accounts for branching between stages in path

on path off pathC Cb

+on path off path

on path

B b= ∏ h BH=∏Note:

• Now we compute the path efforti

B b= ∏ ii

h BH=∏Note:

F GBH=

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Multistage DelaysMultistage Delays

• Path Effort Delay: F iD f= ∑Path Effort Delay:

• Path Parasitic Delay:

F iD f∑

P p= ∑• Path Parasitic Delay:

• Path Delay:

iP p= ∑

D d D P+∑• Path Delay: i FD d D P= = +∑

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Minimizing Delay along a Pathg y g

• Consider two stage pathConsider two stage path( ) ( )1 1 1 2 2 2D g h p g h p= + + +

CH h h= =1 21C

( )1 1 1 2 11

HD g h p g ph

⎛ ⎞= + + +⎜ ⎟

⎝ ⎠0D H∂

2 31 2

,C Ch hC C

= =1 2 2

1 1 2 2

0g gh h

g h g h

∂= − =

Key result of logical effort: Delay is smallest when each stage bears same effort!

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Designing Fast Circuitsg g

• For smallest path delayp y1ˆ N

i if g h F= =

• Thus the minimum delay of a N-stage path is1ND NF P+

• The minimum delay calculation does not require l l i i !

ND NF P= +

calculating gate szies !

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Calculating the Gate SizesCalculating the Gate Sizes

• How wide should the gates be for the least delay?How wide should the gates be for the least delay?

ˆ outCf gh g= = ⇒ ii outg CC =

• Working backward apply the capacitance

inCf gh g= = ⇒ ˆiinCf

• Working backward, apply the capacitance transformation formula to find the input capacitance of each gate given its outputo e c g e g ve s ou pu

• Check your work by verifying the input capacitance specification is met

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Example: 3-stage pathExample: 3 stage path

• Select gate sizes x and y for least delay from A to BSelect gate sizes x and y for least delay from A to B

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Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27Electrical Effort H = 45/8Branching Effort B = 3 * 2 = 6Path Effort F = GBH = 125Best Stage EffortParasitic Delay P = 2 + 3 + 2 = 7

3ˆ 5f F= =

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yDelay D = 3*5 + 7 = 22 = 4.4 FO4

• Work backward for sizesWork backward for sizesy = 45 * (5/3) / 5 = 15x = (15*2) * (5/3) / 5 = 10x (15 2) (5/3) / 5 10

P: 4P: 4N: 4 P: 4

N: 6 P: 12N: 3

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Best Number of Stagesg

• How many stages should a path use?How many stages should a path use?– Minimizing the number of stages is not always the fastest

• Example: drive 64-bit data path with unit inverterExample: drive 64 bit data path with unit inverter

F = GBH = 1 1 64

1 1 1 1

8 4 2.8

Initial Driver

F GBH 1.1.64D = NF1/N + P

= N(64)1/N + N16 8

= N(64) + N 23

64 64 64 64Datapath Load

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N:f:D:

42.815.3

Fastest34

Derivation for Best Number of Stagesg

• Consider adding inverters to the end of a path with n1Consider adding inverters to the end of a path with n1stages– How many inverters give the least delay?

i invD NF p N n p= + + −∑1i=

ln 0N N Ninv

D F F F pN

∂= − + =

∂( )

( ) ( )ln

' ' ' 'lg g f g

fg f g fg

gf f f f

⎛ ⎞⎜ ⎟

Recall differentiation rules:

• Define best stage effort: Th

( )1 l 0

1NFρ =

( ) ( )ln' ' ' 'lng g f g gf e f f g ff

⎛ ⎞= = +⎜ ⎟

⎝ ⎠

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• Then ( )1 ln 0invp ρ ρ+ − =

Best Stage EffortBest Stage Effort

• has no closed-form solution( )1 ln 0p ρ ρ+ − = has no closed form solution

• Neglecting parasitics (p = 0) we find ρ = 2 718

( )1 ln 0invp ρ ρ+ =

• Neglecting parasitics (pinv 0), we find ρ 2.718 (e)

• For pi = 1 solve numerically to get ρ = 3 59For pinv 1, solve numerically to get ρ 3.59.• Should we add additional inverters at the beginning

or at the end ?o e e d ?

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Sensitivity Analysisy y

• How sensitive is delay to using exactly the best y g ynumber of stages?

1.151.26

(ρ =2.4)(ρ=6)

1.0 2.00.5 1.40.7

• 2.4 < ρ < 6 gives delay within 15% of the optimal– We can be sloppy!

Let’s use ρ = 4 logN F→ =

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– Let s use ρ = 4

4logN F→ =

Gate Sizes and DelayGate Sizes and Delay

G = 1*6/3*1 = 2, B = 8*1*1=8, H = 96/10=9.6Path Effort: F = GBH = 153.6Stage Effort: 1/ 3ˆ 5.36f F= =

ˆPath Delay:Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7

A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

ˆ3 1 4 1 22.08D f= + + + =

A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10

word[0]

96 units of wordline capacitance

M. Pedram USC/EEword[15]

96 units of wordline capacitance

ComparisonComparison

• Compare many alternatives with a spreadsheetCompare many alternatives with a spreadsheetDesign N G P DNAND4-INV 2 2 5 29.8NAND2-NOR2 2 20/9 4 30.1INV-NAND4-INV 3 2 6 22.1

A 4 4 2 21 1NAND4-INV-INV-INV 4 2 7 21.1NAND2-NOR2-INV-INV 4 20/9 6 20.5NAND2-INV-NAND2-INV 4 16/9 6 19.7INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4NAND2-INV-NAND2-INV-INV-INV

6 16/9 8 21.6

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Review of Definitions

Term Stage PathTerm Stage Pathnumber of stageslogical effort iG g= ∏

gelectrical effortbranching effort

i∏out-path

in-path

iB b= ∏

on-path off-path

on-path

C CCb +=

efforteffort delay

F GBH=

F iD f= ∑f gh=

parasitic delaydelay

iP p= ∑i FD d D P= = +∑

d f p= +

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Deriving the Method of Logical Effortg g

( )d kR C C( )abs gate out pd kR C C= +

outb t i t tt

Cd R C R Cκ κ⎛ ⎞

= +⎜ ⎟⎜ ⎟ in

out,,,

abs gate in gate p gategatein gate

d R C R CC

κ κ+⎜ ⎟⎜ ⎟⎝ ⎠

R C R Cd C⎛ ⎞

Cin,gate Cp,gate Cout

gate in gate gate p gateabs out

t t t t in t tgate

R C R Cd CR C R C C R C

κ κκ κ κ

⎛ ⎞= +⎜ ⎟⎜ ⎟

⎝ ⎠

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Deriving the Method of Logical Effortg g

R C R Cd Cκ κ⎛ ⎞, ,

gate in gate gate p gateabs out

t t t t in t tgate

R C R Cd CR C R C C R C

κ κκ κ κ

⎛ ⎞= +⎜ ⎟⎜ ⎟

⎝ ⎠

,gate in gate

=d gh p= +

in gate

gate p gate

,gate p gate

M. Pedram USC/EE 42t t

τ κ=

Re-Computing Logical EffortRe Computing Logical Effort

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Review Method of Logical EffortReview Method of Logical Effort

1) Compute path effort F GBH=1) Compute path effort2) Estimate best number of stages3) Sketch path with N stages

F GBH=

4logN F=

3) Sketch path with N stages4) Estimate least delay5) Determine best stage effort

1ND NF P= +

1ˆ Nf F5) Determine best stage effort6) Find gate sizes

i outin

M. Pedram USC/EE 44

Designing Super Bufferg g p

• How many stages should a path use?How many stages should a path use?– Minimizing the number of stages is not always the fastest

• Example: drive 64-bit data path with unit inverterExample: drive 64 bit data path with unit inverter

F = GBH = 1 1 64

1 1 1 1

8 4 2.8

Initial Driver

F GBH 1.1.64D = NF1/N + P

= N(64)1/N + N16 8

= N(64) + N 23

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N:f:D:

42.815.3

Fastest45

Designing Super Buffer

• 1 Stage

1 Stage1 1 1 1

8 4 2.8

Initial Driverˆ 641*64 1*1 65

= == + =

• 2 Stages 16 8

2 2 64 82*8 2*1 18

= = == + =

• 3 Stages N:f:D:

42.815.3

Fastest3 3ˆ 64 43*4 3*1 15

= = =+

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3*4 3*1 15d = + =

Sensitivity Analysisy y

• How sensitive is delay to using exactly the best y g ynumber of stages?

1.151.26

(ρ =2.4)(ρ=6)

1.0 2.00.5 1.40.7

• 2.4 < ρ < 6 gives delay within 15% of the optimal– We can be sloppy!

Let’s use ρ = 4 logN F→ =

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– Let s use ρ = 4

4logN F→ =

Using the Wrong Number of StagesUsing the Wrong Number of Stages

• If effort is between 2 and 8, the design will be withinIf effort is between 2 and 8, the design will be within 35% of the best delay

• If effort is between 2.4 and 6, the design will be within , g15% of the best delay– Stage effort of 4 produces within 2% of minimum

• Avoid using excessively large stage effort since it results in slow rise and fall times and “hot electron” problems occur since, greatest damage occurs to NMOS in saturation

B tt t t th t f

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– Better use too many stages than too few

Example: 3-stage path (revisited)p g p ( )

ˆ22 1 2 63D f= =5

22.1 2.63ˆ21.4 3.34

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27Electrical Effort H = 45/8Branching Effort B = 3 * 2 = 6Path Effort F = GBH = 125Best Stage EffortParasitic Delay P = 2 + 3 + 2 = 7

3ˆ 5f F= =

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yDelay D = 3*5 + 7 = 22 = 4.4 FO4

Using the Wrong Gate Sizeg g

• For s ranging from 0.5 to 2, the actual delay is within 15% of the minimum

• For s in the range of 2/3 to 1.5, the actual delay is within 5% of the minimum

Th d i h d l f f d l i– The designer has great deal of freedom to select gate sizes

• Standard cell libraries with limited repertoire of gate sizes can achieve acceptable performance

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sizes can achieve acceptable performance

ExampleExample

• Decoder specifications:A[3:0] A[3:0]

32 bits

Decoder specifications:– 16 word register file– Each word is 32 bits wide

16 words

4:16 Decoder

Register File

– Each bit presents load of 3 unit-sized transistors– True and complementary address inputs A[3:0]– Each input may drive 10 unit-sized transistors

• Use LE to decide:– How many stages to use?– How large should each gate be?

H f t d d t ?

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– How fast can decoder operate?

ExampleExample

• Decoder effort is mainly electrical and branchingDecoder effort is mainly electrical and branchingElectrical Effort: H = (32*3) / 10 = 9.6Branching Effort: B = 8Branching Effort: B 8

• If we neglect logical effort (assume G = 1)Path Effort: F = GBH = 76 8Path Effort: F = GBH = 76.8Number of Stages: N = log4F = 3.1T 3 t d iTry a 3-stage design

76 8 4 3

M. Pedram USC/EE 52

76.8 4.3= =

Asymmetric Gatesy

• Values of s between 0 and 0.5Values of s between 0 and 0.5 favor input A

• Values of s between 0.5 and 1 A

favor input BB

s11 2+

1 11 1 =

1 11 1

M. Pedram USC/EE 53

Asymmetric Gates: Total logical Efforty g

• To compare the logical effort of anTo compare the logical effort of an asymmetric gate with that of symmetric gate we use total logical Y

effort, defined as follows: A

( )1 4

• For s = 0.01, which minimizes the

Bs1( )1

s sg =

LE of A input, we have:,

1, 34,35

tot asymmetric

≈ ≈=

M. Pedram USC/EE 54

,4 82*3 3tot symmetricg = =

Asymmetric Gates (Cont’d)y ( )

• Extremely asymmetric designs (e.g. s = 0.01) are notExtremely asymmetric designs (e.g. s 0.01) are not desirable– total logical effort enormous.– huge size of pulldown transistor, layout problems

• Less extreme asymmetry is more practical– s = 0.25

1.1, 2,3.1

tot asymmetric

– The pulldown Transistor sizes are 4/3 and 4, respectively, 2.67tot symmetricg =

M. Pedram USC/EE 55

Applications of Asymmetric Gatespp y

• Assume that one signal path isAssume that one signal path is unusually slow (e.g., reset_bar)

• The 1st stage should have the goutput drive of 12/6 inverter

• Take advantage of slow gresponse allowed to changes on reset i.e., make the PMOS as small as possible

7 12 1.056 12Ag +

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Logical Effort of Pseudo NMOS Logicg g

• Calculate the logical effort of a pseudo NMOS NOR2Calculate the logical effort of a pseudo NMOS NOR2

rising4LE = falling

4 43R C

LE = =

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rising 3 falling 3 9RC

Logical Effort of Dynamic Logicg y g

• Logical effort of a dynamic inverterLogical effort of a dynamic inverter

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Logical Effort of Dynamic Logicg y g

• Logical effort of dynamic NAND2Logical effort of dynamic NAND2

3 * 1R Cg = =2 * 2R Cg = =

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= = *3 3g

R C= =

Logical Effort of Domino Logicg g

• F= ab+cF ab+c

a 2 1/2

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Logical Effort of Domino Logicg g

• Best effort for Static = 4Best effort for Static 4• Best effort for Dynamic = 2 to 2.75

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Fixed Side-Load Problem

• Size gates assuming Cw=0• Add Cw and resize pre-chain• Resize post-chain• Repeat pre-chain and post-chain resizing till the

delay value converges

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Fixed Side Load Problem (Cont’d)( )

Cin1641

16 256+16 2564 4 3 794

delay += + + + =

( )4log 272 4N ≈ ≈In the pre-chain CL=256+16=272

( )4 4 4 5 25delay = + + =

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Fixed Side Load Problem (Cont’d)( )

R i h iResize post-chain

( )256 64+( ) ( )256 643 4 1 5 23

64delay

+= + + + =

Make X bigHow to size the gate X ?

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Limits of the Logical Effort based O i i iOptimization

• Simplistic delay modelp y– Neglects input rise/fall time effects (has been extended)

• Interconnect– Iteration required in designs with large interconnect

capacitances

• Path-based optimization– Too many paths

Si i b d h fli i h i i b d– Sizing based on one path may conflict with sizing based on another path

• So far provides the maximum speed solution only

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• So far provides the maximum speed solution only– Not minimum area/power under constrained delay (see next)

Delay-Constrained Area OptimizationDelay Constrained Area Optimization

• Given:– Maximum allowed capacitive load Cin on the source– A single sink with capacitive load CL

– A required time T

• Find– Optimum number of inverters and their sizing so as to

minimize the inverter chain area while meeting the constraintsconstraints

min. . ( )

Areas t i delay T≤

C1 C2 Cn

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( )( ) in

yii C C≤

Area Optimization: Problem Formulationp

• The problem can be stated as follows:The problem can be stated as follows:

∑ =∝ ni iCnArea 1)(

h1 h2 hn

CL∑ =i i1)(

= nij j

hCC ∑

∝ ni n

hCnArea 1)(

( )1 1

n ni ii i

delay p h np h= =

= + = +∑ ∑

∏ =ij j

CMinh=

∑∏

Lnj jinn

hCC ≥→≤= ∏

∏ ==

1 1. . : ( )

s t I h T np

CII H h

=≤ −

≡ ≥

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1( ) L

II H hC=

≡ ≥∏

Area Optimization: SolutionArea Optimization: Solution

• To find the “best” inverter chain, the problem should be solved for all values

For all don L

h=∑∏solved for all values

of n• There are ways to 1

. . : ( )

s t I h T np

=≤ −

∏∑

bound n between an nmin and nmax, but we will not discuss them

Choose best ;

CII hC

=≥∏

will not discuss them here

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An Important ObservationAn Important Observation

• It can be shown that when the delay constraint isIt can be shown that when the delay constraint is loose, in the optimal solution of minimum area inverter chain:

where h0=0 and h1 can be found from:

)1( 11 +−= −+ iiii hhhh (*)

h T np=

= −∑I (*) h l f h ’ i ll• In recurrence (*) the values of hi’s grow exponentially– Cin=1, CL=90, T=23, n=4

h =1 h =2 h =4 h =12

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h1=1, h2=2, h3=4, h4=12

3 logical effort module

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logical effort: designing fast cmos...

logical functions x10 module - zennio

logical effort

module logical functions x10 - zennio

module 2 designing a logical database model

lecture 6: logical effort

logical effort - the college of engineering at the

logical effort based dual mode logic gates

chap4 lect11 logical effort

module 2 designing a logical database model. module overview...

logical effort reese version

module 4 - logical operations

logical effort - designing fast cmos circuits sutherland...

lecture 6: logical effort - university of...

chapter 4 calculating the logical effort of...

6. logical effort