2-pad digital beamformer chris shenton 11 th october 2007
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2-PAD Digital BeamformerChris Shenton 11th October 2007
2-PAD Digital Beamformer2-PAD Digital Beamformer
Chris ShentonChris Shenton
1111thth October 2007 October 2007
2-PAD Digital BeamformerChris Shenton 11th October 2007
ObjectivesObjectives
Implement an example of a fully digital beamforming system.
Initially a 4x4 receiving element array, scalable up to 8x8 elements.
– Can go much bigger with more hardware.
– Set modest initial performance targets.
– With expectations to do A LOT better as we explore optimisation options.
Fully scalable architecture with a high degree of platform independence.
Use it to develop software methodology.
2-PAD Digital BeamformerChris Shenton 11th October 2007
2-PAD Beamformer Processing Architecture2-PAD Beamformer Processing Architecture
Large number of simple high performance processing elements;
Connected together via very high bandwidth links.
Processing element means;
on-chip – thread unit or similar operational unit
off-chip – multiple devices
Concept is valid for both intra-chip and inter-chip communications
Key Point: The problem is data movement NOT MFLOPS.
2-PAD Digital BeamformerChris Shenton 11th October 2007
Continued...Continued...
• Software development methodologies for multi-processor systems
are not yet defined but are happening (e.g PS3 Cell Processor).
• Difficult problem will have to be solved by the major silicon vendors,
we will see the benefit of this effort by intercepting these new
methods.
• This is the future of computing for both scientific and mass market
computing.
2-PAD Digital BeamformerChris Shenton 11th October 2007
Continued...Continued...
– We need to obtain very high density processing to meet power and cost
objectives.
– Possible implementation options include;
ASIC – Very high density, lowest power, lowest cost
FPGA – Flexibilty, medium density, high power, high cost.
MPU/GPU – Flexibility, medium density, medium power, medium cost
– Start simple with simple Units of Design deployed sparsely on commercially
available processor technology.
2-PAD Digital BeamformerChris Shenton 11th October 2007
Increasing The Processing Capacity of 2-PAD.Increasing The Processing Capacity of 2-PAD.
• Scalable Architecture in 3 dimensions
• 2-PAD Initial implementation has low processing
density vs hardware resource.
• Blue area represents initial 4x4 element design
• Yellow area represents scale up to 8x8 elements.
2-PAD Digital BeamformerChris Shenton 11th October 2007
So What Are We Building Then?So What Are We Building Then?
GbE
20Gb/s32Gb/s
2x8Gb/s
2-PAD Digital BeamformerChris Shenton 11th October 2007
Data Acquisition CardData Acquisition Card
Xilinx XC5VLX110T
FF1736 42.5mm x 42.5 mm
XAUIDeSerialiserBW
Processing
Dual ADC
2 x 1.0Gs/s
9.6Gb/s
XAUIDeSerialiserBW
Processing
Sampler Card
Infiniband
Connector
4X
Use all 8
Lanes for
TX
10Gb/s
XAUI-CX4
PMC Sierra
QuadPHY-XR
Clock
Management
Serial PROM
FPGA
Configuration
Instrument
Management
Subsystem
RJ45
Sig
na
l Ro
utin
g
Power
Management
9.6Gb/s 10Gb/s
VHDM
Backplane
Connector
System
RS485
Channel
Conditioning
Channel
Conditioning
Signal Conditioning
Mezzanine Card
RJ45
HM-Zd
Backplane
Connector
System
20Gb/s
2-PAD Digital BeamformerChris Shenton 11th October 2007
Processor Interface Card.Processor Interface Card.
Xilinx XC5VLX110T
FF1136 35mm x 35mm
XAUI
XAUI
Data
Formatting
DDR2
Style
Interface
Multi-Core
Processor
500Mb/s
x 64 pins
32 Gb/s
Blade Mezzanine Card
XAUI-CX4Transwitch
TransPHY-CX4
or
PMC Sierra
QuadPHY-XR
Infiniband
Connector
4X
uses all 8
lanes for
RX
500Mb/s
x 64 pins
32 Gb/sXAUI
XAUI
Data
Formatting
DDR2
Style
Interface
XAUI-CX4Transwitch
TransPHY-CX4
or
PMC Sierra
QuadPHY-XR
XAUI-CX4Transwitch
TransPHY-CX4
or
PMC Sierra
QuadPHY-XR
XAUI-CX4Transwitch
TransPHY-CX4
or
PMC Sierra
QuadPHY-XR
VH
DM
Mez
zani
ne C
onne
ctor
20Gb/s
20Gb/s
Processing Blade Base Card (Simplified)
10Gb/s
10Gb/s
10Gb/s
10Gb/s
10Gb/s 10Gb/s
10Gb/s 10Gb/s
10Gb/s
10Gb/s
10Gb/s
10Gb/s
Serial
PROM
FPGA
Configuration
Infiniband
Connector
4X
uses all 8
lanes for
RX
DDR2
Memory
DDR2
Memory
Backplane
Connector
2-PAD Digital BeamformerChris Shenton 11th October 2007
SummarySummary
• Digital Beamforming is as much an issue of inter-
processor bandwidth than raw FLOPs.
• Cost of Multi-core Processors will fall in the medium term.
• Improvements in software development methodologies
will have to happen.
• 2-PAD Will demonstrate fundamental architectural
concepts with options for future cost & power reduction.
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