1 engg 1203 tutorial combinational logic (ii) and sequential logic (i) 8 feb learning objectives ...

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ENGG 1203 Tutorial

Combinational Logic (II) and Sequential Logic (I) 8 Feb Learning Objectives

Apply Karnaugh map for logic simplification Design a finite state machine

News HW1 (Feb 22, 2013, 11:55pm)

Ack.: HKU ELEC1008, ISU CprE 281x, PSU CMPEN270, Wikipedia

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Simplify the Boolean expression of the circuit Change each NAND gate in the circuit to a NOR

gate, and simplify the Boolean expression of the circuit

MNQ

x

Simplification using K-map

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M N Q x

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

01101

01000

10110100NQ

M

B

C

AMNQ

x

x MQ NQ

From truth table to K-map

Solution (a)

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M N Q x

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

11101

01100

10110100NQ

M

B

C

AMNQ

x

x MN Q

Solution (b)

Finite State Machine (FSM)

State transition diagram Truth table K-Map Circuit

State Present state: before the register Next state: after the register State transition: during clock 2n states: n FFs

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Turnstile – Control access Depositing a token in a slot on the turnstile

unlocks the arms, allowing a single customer to push through.

After the customer passes through, the arms are locked again until another coin is inserted.

A simple Finite State Machine (FSM)

Current State Input Next State Output

Lockedcoin Unlocked Release turnstile so customer can push through

push Locked None

Unlockedcoin Unlocked None

push Locked When customer has pushed through, lock turnstile

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A simple FSM

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State Transition Transition condition

Arm: 0 Arm: 1

Current State Input Next State Output

Lockedcoin Unlocked Release turnstile so customer can push through

push Locked None

Unlockedcoin Unlocked None

push Locked When customer has pushed through, lock turnstile

Specification FSM

Steps in designing a state machine Draw a state transition diagram

An initial state Other states to keep track of various activities Transitions

Generate a state transition table and a output table Write state transition table and output table in binary

State assignment, i.e., the code used for each state

Derive canonical sum-of-product expressions Draw the circuit

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From state transitiondiagram to truth table Four states Two-bit state q: Present state q*: Next state z: Output

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Condition/Output

From truth table to K-map

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DA DB DA DBA B

From K-map to circuit

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Logic for state transition

State register Logic for output

A simple FSM design

Design a state machine that will repeatedly display in binary values 1 (001), 3 (011), 5 (101), and 7 (111) How many states we need? S0, S1, S2, S3

Simplified state transition diagram?

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Solution

Output table

L2 = XY'+XY = X

L1 = X'Y+XY = Y

L0 = X'Y'+X'Y+XY'+XY = 1 State transition table

X = X'Y+XY'

Y = X'Y+XY' = Y'

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Current state Output

S0 (00) 1 (001)

S1 (01) 3 (011)

S2 (10) 5 (101)

S3 (11) 7 (111)

Current Output

X Y L2 L1 L0

0 0 0 0 1

0 1 0 1 1

1 0 1 0 1

1 1 1 1 1

Current state Next state

S0 (00) S1 (01)

S1 (01) S2 (10)

S2 (10) S3 (11)

S3 (11) S0 (00)

Current Next

X Y X Y

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

A complicated FSM design

Vending Machine Collect money, deliver product and change

Vending machine may get three inputs Inputs are nickel (5c), dime (10c), and quarter (25c) Only one coin input at a time Product cost is 40c Does not accept more than 50c Returns 5c or 10c back Exact change appreciated

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Solution

We are designing a Mealy state machine (i.e., output depends on both current state and inputs).

Suppose we ask the machine to directly return the coin if it cannot accept an input coin.

Input specification: I1 I2 Represent the coin inserted 00 - no coin (0 cent), 01 – nickel (5 cents), 10 – dime (10 cents),

11 – quarter (25 cents)

Output specification: C1C2P C1C2 represent the coin returned – 00, 01, 10, 11 P indicates whether to deliver product – 0, 1

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Solution

States: S1S2S3 Represent the money inside the machine now 3 bits are enough to encode the states

S00 (0 cents) – 000 S05 (5 cents) – 001 S10 – 010 S15 – 011 S20 – 100 S25 – 101 S30 – 110 S35 – 111

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Solution

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Solution

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S3511/110 S3510/011 S00 01/001 S00

11/11011/00001/00010/000

S35: Currently the machine has 35 cents e.g. 11/110 : If we insert a quarter (11), then the machine

should return one quarter and zero product (110) 35c (35 cents inside the machine now) + 25c (insert 25 cents)

= 35c (35 cents inside the machine in the next state) + 25c (return 25 cents) + 0c (return no product)

Input

Output

Next state

00/000 S35

Solution

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S3511/110 S3510/011 S0001/001 S00

11/11011/00001/00010/000

e.g. 10/011: If we insert a dime (10), then the machine should return one nickel and one product (011) 35c (35 cents inside the machine now) + 10c (insert 10 cents)

= 0c (zero cent inside the machine in the next state) + 5c (return 5 cents) + 40c (return one product)

e.g. 01/001: If we insert a nickel (01), then the machine should return zero coin and one product (001) 35c (35 cents inside the machine now) + 5c (insert 5 cents)

= 0c (zero cent inside the machine in the next state) + 0c (return zero cent) + 40c (return one product)

00/000 S35

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(Appendix) Simplification using K-map Simplify the following Boolean expressions using

Karnaugh map.

i)

ii)

A B A B

B BC ABC AB

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Solution

A/B 0 1

0 0 0

1 1 1

A/BC 00 01 11 10

0 0 0 1 1

1 1 1 1 1

B BC

ABC AB

B A

i)

ii)

A B A B A

(Appendix) Counter

Figure a) shows a complete four-bit parallel adder with registers and b) shows the signals used to add binary numbers from memory and store their sum in the accumulator. Suppose the numbers being added are 1001 and 0101. Also assume that Co=0. Describe what happen at t1, t2, t3, t4 and t5.

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Solution

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At time t1, is active low FF at the bottom will be cleared

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At time t2, load is active high Set A numbers will be loaded into the upper register

At time t3, transfer is active high Adder process between A3A2A1A0 = 0000 and B3B2B1B0 = 1001

The sum S3S2S1S0 = 1001 are transferred to register A on PGT due to this transfer pulse at t3

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At time t4, the load is active high, the set B numbers will be loaded into register B on PGT of LOAD pulse B3B2B1B0 = 0101

At time t5, A3A2A1A0 = 1001 and B3B2B1B0 = 0101, the adder produces S3S2S1S0 = 1110. This sum is transferred into register A when TRANSFER pulse occur at t5.

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(Appendix) State changing in FSM Design a 2-bit counter with input x that can be

A down counter when x = 0 (…1110010011…) A Johnson counter when x = 1 (…0001111000…)

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Solution

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(Appendix) A typical FSM

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FSM Truth table Circuit

Logic for output

Logic for state transition

State register