1 ee/cpre 465 memory array subsystems. 2 outline memory arrays sram architecture –sram cell...

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EE/CPRE 465

Memory Array Subsystems

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Outline• Memory Arrays• SRAM Architecture

– SRAM Cell

– Decoders

– Column Circuitry

– Multiple Ports

• DRAM Architecture– DRAM Cell

– Bitline architectures

• ROM• Serial Access Memories

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Memory ArraysMemory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory(CAM)

Read/Write Memory(RAM)

(Volatile)

Read Only Memory(ROM)

(Nonvolatile)

Static RAM(SRAM)

Dynamic RAM(DRAM)

Shift Registers Queues

First InFirst Out(FIFO)

Last InFirst Out(LIFO)

Serial InParallel Out

(SIPO)

Parallel InSerial Out

(PISO)

Mask ROM ProgrammableROM

(PROM)

ErasableProgrammable

ROM(EPROM)

ElectricallyErasable

ProgrammableROM

(EEPROM)

Flash ROM

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Array Architecture

n=4m=2k=1

• 2n words of 2m bits each• If n >> m, fold by 2k into fewer rows of

more columns• Good regularity – easy to design• Very high density if good cells are used

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12T SRAM Cell• Basic building block: SRAM Cell

– Holds one bit of information, like a latch– Must be read and written through bitline

• 12-transistor (12T) SRAM cell– Use a simple latch connected to bitline– 46 x 75 unit cell

bit

write

write_b

read

read_b

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6T SRAM Cell• Cell size accounts for most of array size

– Reduce cell size at expense of complexity

• 6T SRAM Cell– Used in most commercial chips– Data stored in cross-coupled inverters

• Read:– Precharge bit, bit_b– Raise wordline

• Write:– Drive data onto bit, bit_b– Raise wordline

bit bit_b

word

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SRAM Read

• Precharge both bitlines high• Then turn on wordline• One of the two bitlines will

be pulled down by the cell• Ex: A = 0, A_b = 1

– bit discharges, bit_b stays high

– But A bumps up slightly

• Read stability– A must not flip

– N1 >> N2

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600

time (ps)

word bit

A

A_b bit_b

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SRAM Write• Drive one bitline high,

the other low• Then turn on wordline• Bitlines overpower cell with

new value• Ex: A = 0, A_b = 1,

bit = 1, bit_b = 0– Force A_b low, then A rises high

• Writability– Must overpower feedback inverter

– N4 >> P2time (ps)

word

A

A_b

bit_b

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600 700

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

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SRAM Sizing• High bitlines must not overpower inverters during reads• But low bitlines must write new value into cell

bit bit_b

med

A

weak

strong

med

A_b

word

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SRAM Column ExampleRead Write

H H

SRAM Cell

word_q1

bit_v1f

bit_b_v1f

out_v1rout_b_v1r

1

2

word_q1

bit_v1f

out_v1r

2

MoreCells

Bitline Conditioning

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MoreCells

SRAM Cell

word_q1

bit_v1f

bit_b_v1f

data_s1

write_q1

Bitline Conditioning

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SRAM Layout• Cell size is critical: 26 x 45 (even smaller in industry)

• Tile cells sharing VDD, GND, bitline contacts

VDD

GND GNDBIT BIT_B

WORD

Cell boundary

Thin Cell• In nanometer CMOS

– Avoid bends in polysilicon and diffusion

– Orient all transistors in one direction

• Lithographically friendly or thin cell layout fixes this– Also reduces length and capacitance of bitlines

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Commercial SRAMs• Five generations of Intel SRAM cell micrographs

– Transition to thin cell at 65 nm

– Steady scaling of cell area

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Decoders• n:2n decoder consists of 2n n-input AND gates

– One needed for each row of memory– Build AND from NAND or NOR gates

Static CMOS Pseudo-nMOS

word0

word1

word2

word3

A0A1

A1

word

A0 1 1

1/2

2

4

8

16word

A0

A1

1

1

11

4

8

word0

word1

word2

word3

A0A1

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Decoder Layout• Decoders must be pitch-matched to SRAM cell

– Requires very skinny gates

GND

VDD

word

buffer inverterNAND gate

A0A0A1A2A3 A2A3 A1

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Large Decoders• For n > 4, NAND gates become slow

– Break large gates into multiple smaller gates

word0

word1

word2

word3

word15

A0A1A2A3

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Predecoding• Many of these gates are redundant

– Factor out common

gates into predecoder

– Saves area

– Same path effortA0

A1

A2

A3

word1

word2

word3

word15

word0

1 of 4 hotpredecoded lines

predecoders

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Column Circuitry• Some circuitry is required for each column

– Bitline conditioning

– Sense amplifiers

– Column multiplexing

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Bitline Conditioning• Precharge bitlines high before reads

• Equalize bitlines to minimize voltage difference when using sense amplifiers

bit bit_b

bit bit_b

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Sense Amplifiers• Bitlines have many cells attached

– Ex: 32-kbit SRAM has 256 rows x 128 cols

– 128 cells on each bitline

• tpd (C/I) V– Even with shared diffusion contacts, 64C of diffusion

capacitance (big C)

– Discharged slowly through small transistors (small I)

• Sense amplifiers are triggered on small voltage swing (reduce V)

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Differential Pair Amp• Differential pair requires no clock• But always dissipates static power

bit bit_bsense_b sense

N1 N2

N3

P1 P2 Current mirroras high impedance load

Current source

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Clocked Sense Amp• Clocked sense amp saves power• Requires sense_clk after enough bitline swing• Isolation transistors cut off large bitline capacitance

bit_bbit

sense sense_b

sense_clk isolationtransistors

regenerativefeedback

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Twisted Bitlines• Sense amplifiers also amplify noise

– Coupling noise is severe in modern processes

– Try to couple equally onto bit and bit_b

– Done by twisting bitlines

b0 b0_b b1 b1_b b2 b2_b b3 b3_b

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Column Multiplexing• Recall that array may be folded for good aspect ratio• Ex: 2k word x 16 bit folded into 256 rows x 128

columns– Must select 16 output bits from the 128 columns

– Requires 16 8:1 column multiplexers

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Tree Decoder Mux• Column mux can use pass transistors

– Use nMOS only, precharge outputs

• One design is to use k series transistors for 2k:1 mux– No external decoder logic needed

B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7A0

A0

A1

A1

A2

A2

Y Yto sense amps and write circuits

2:1 MUX

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Single Pass-Gate Mux• Or eliminate series transistors with separate decoder

A0A1

B0 B1 B2 B3

Y

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Example: 2-way Muxed SRAM

MoreCells

word_q1

write0_q1

2

MoreCells

A0

A0

2

data_v1

write1_q1

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Multiple Ports• We have considered single-ported SRAM

– One read or one write on each cycle

• Multiported SRAM are needed for register files• Examples:

– Multicycle MIPS must read two sources or write a result on some cycles

– Pipelined MIPS must read two sources and write a third result each cycle

– Superscalar MIPS must read and write many sources and results each cycle

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Dual-Ported SRAM• Simple dual-ported SRAM

– Two independent single-ended reads

– Or one differential write

• Do two reads and one write by time multiplexing– Read during ph1, write during ph2

bit bit_b

wordBwordA

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Multi-Ported SRAM• Adding more access transistors hurts read stability• Multiported SRAM isolates reads from state node• Single-ended design minimizes number of bitlines

4 read ports3 write ports

Large SRAMs• Large SRAMs are split into subarrays for speed• Ex: UltraSparc 512KB cache

– 4 128 KB subarrays

– Each have 16 8KB banks

– 256 rows x 256 cols / bank

– 60% subarray area efficiency

– Also space for tags & control

[Shin05]

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Dynamic RAM (DRAM)• Store contents as charge on a capacitor• 1 transistor and 1 capacitor per cell

• Order of magnitude greater density but much higher latency than SRAM

• Cell must be periodically read and refreshed so that its contents do not leak away

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DRAM Cell Read Operation• Bitline is first precharged to VDD/2• Charge sharing between cell and

bitline causes a voltage change V in bitline

• Cell must be rewritten after each read

bitcell

cellDD

CC

CVV

2

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Trench Capacitor• Cell must be small to achieve high density• Large cell capacitance is essential to provide a

reasonable voltage swing and to minimize soft errors

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Subarray Architectures• Size represents a tradeoff between density and performance

– Larger subarray amortize the decoders and sense amplifers– Small subarray are faster and have larger bitline swings because of smaller

wordline and bitline capacitance

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Bitline ArchitecturesOpen Folded

Twisted

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Two-Level Addressing Scheme• DRAM uses a two-level decoder

– Row access: choose one row by activating a word line– Column access: select the data from the column latches

• To save pins and reduce package cost, the same address lines can be used for both the row and column addresses– Control signals RAS (Row Access Strobe) and CAS (Column Access

Strobe) are used to signal which address is being supplied– Refresh one row in each cycle

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Sychronous DRAM • For each row access:

– An entire row is copied to column latches

– Only a few bits (= data width) are output

– All the others are thrown away!

• Sychronous DRAM (SDRAM):– Allow the column address to change without changing the row

address -- this feature is called page mode

– Enable the transfer a burst of data from a series of sequential addresses

• A burst is defined by a starting address and a burst length

– Double Data Rate (DDR) SDRAM – data are transferred on both the rising and falling edge of an externally supplied clock (up to 300 MHz in 2004)

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Read-Only Memories• Read-Only Memories are nonvolatile

– Retain their contents when power is removed

• Mask-programmed ROMs use one transistor per bit– Presence or absence determines 1 or 0

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ROM Example• 4-word x 6-bit ROM

– Represented with dot diagram

– Dots indicate 1’s in ROMWord 0: 010101

Word 1: 011001

Word 2: 100101

Word 3: 101010

ROM Array

2:4DEC

A0A1

Y0Y1Y2Y3Y4Y5

weakpseudo-nMOS

pullups

Looks like 6 4-input pseudo-nMOS NORs

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ROM Array Layout• Unit cell is 12 x 8 (about 1/10 size of SRAM)

UnitCell

GND

word0

word1

word2

word3

bit5 bit4 bit3 bit2 bit1 bit0

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Row Decoders• ROM row decoders must pitch-match with ROM

– Only a single track per word!

VDD GND

A0 ~A0 A1 ~A1 A0 ~A0 A1 ~A1

word3

word2

word1

word0

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Complete ROM Layout

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PROMs and EPROMs• Programmable ROMs

– Build array with transistors at every site– Burn out fuses to disable unwanted transistors

• Electrically Programmable ROMs– Use floating gate to turn off unwanted transistors– High voltage to upper gate causes electrons to jump through

thin oxide onto the floating gate

n+

p

GateSource Drain

bulk Si

Thin Gate Oxide(SiO2)

n+

PolysiliconFloating Gate

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Electrically Programmable ROMs• EPROM (Erasable Programmable ROM)

– Erased through exposure to UV light that knocks the electrons off the floating gate

• EEPROM (Electrically Erasable Programmable ROM)– Can be erased electrically– Offers fine-grained control over which bits are erased

• Flash– Can be erased electrically– Erase a block at a time– A freshly erased block can be written once, but then cannot be

written again until the entire block is erased again– Economical and convenient– NOR flash or NAND flash

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NOR ROM vs. NAND ROMNOR ROM• Each bitline is a pseudo-nMOS NOR

• The GND line limits the cell size

• As small as 11x7 per cell

NAND ROM• Each bitline is a pseudo-nMOS NAND

• No Vdd/GND line to limit the cell size

• As small as 6x5 per cell

• Delay quadratic to # of series transistors

ROM Array

2:4DEC

A0A1

Y0Y1Y2Y3Y4Y5

weakpseudo-nMOS

pullups

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Layout of NAND ROM• Cell contents are specified by using

either a transistor (0) or a metal jumper (1) in each position

• 7x8per cell

• A transistor in every position

• Extra implanatation step to create a –ve threshold voltage to turn certain transistors permanently ON

• 6x5per cell

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NOR Flash vs. NAND Flash• NOR Flash

– Read almost as fast as DRAM, but long erase and write times– Endurance 10,000 to 1,000,000 erase cycles– A full address/data interface that allows random access– Suitable for storage of data that needs infrequent updates

• Computer BIOS, Firmware of set-top box

• NAND Flash– Higher density, lower cost per bit– Longer read time, but faster erase and write times– 10x the endurance– Limited I/O interface allows only sequential data access– Suitable for mass-storage devices

• E.g., USB Flash drive, Memory card

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SDRAM, NOR / NAND Flash Comparison

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NOR ROM Flash Memory OperationsErase

Write Read

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Building Logic with ROMs• Use ROM as lookup table (LUT) containing truth table

– n inputs, k outputs requires 2n words x k bits

– Changing function is easy – reprogram ROM

• Finite State Machine– n inputs, k outputs, s bits of state

– Build with 2n+s x (k+s) bit ROM and (k+s) bit reg

ninputs

2n w

ord

line

s

ROM Array

k outputs

DE

C ROM

inputs outputs

state

n ks

k

s

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PLAs• A Programmable Logic Array performs any function in

sum-of-products form.• Literals: inputs & complements• Products / Minterms: AND of literals• Outputs: OR of Minterms

• Example: Full Adder

out

s abc abc abc abc

c ab bc ac

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b coutc

Minterm

s

Inputs Outputs

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NOR-NOR PLAs• ANDs and ORs are not very efficient in CMOS• Dynamic or Pseudo-nMOS NORs are very efficient• Use DeMorgan’s Law to convert to all NORs

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

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PLA Schematic & Layout

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b c

outc

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PLAs vs. ROMs• The OR plane of the PLA is like the ROM array• The AND plane of the PLA is like the ROM decoder• PLAs are more flexible than ROMs

– No need to have 2n rows for n inputs

– Only generate the minterms that are needed

– Take advantage of logic simplification

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Serial Access Memories• Serial access memories do not use an address

– Shift Registers

– Tapped Delay Lines

– Serial In Parallel Out (SIPO)

– Parallel In Serial Out (PISO)

– Queues (FIFO, LIFO)

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Shift Register• Shift registers store and delay data• Simple design: cascade of registers

– Watch your hold times!

clk

Din Dout8

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Denser Shift Registers• Flip-flops aren’t very area-efficient• For large shift registers, keep data in SRAM instead• Move read/write pointers to RAM rather than data

– Initialize read address to first entry, write to last

– Increment address on each cycle

Din

Dout

clk

counter counter

reset

00...00

11...11

readaddr

writeaddr

dual-portedSRAM

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Tapped Delay Line• A tapped delay line is a shift register with a

programmable number of stages• Set number of stages with delay controls to mux

– Ex: 0 – 63 stages of delay

SR

32

clk

Din

delay5

SR

16

delay4

SR

8

delay3

SR

4

delay2

SR

2

delay1

SR

1

delay0

Dout

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Serial In Parallel Out• 1-bit shift register reads in serial data

– After N steps, presents N-bit parallel output

clk

P0 P1 P2 P3

Sin

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Parallel In Serial Out• Load all N bits in parallel when shift = 0

– Then shift one bit out per cycle

clkshift/load

P0 P1 P2 P3

Sout

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Queues• Queues allow data to be read and written at different

rates.• Read and write each use their own clock, data• Queue indicates whether it is full or empty• Build with SRAM and read/write counters (pointers)

Queue

WriteClk

WriteData

FULL

ReadClk

ReadData

EMPTY

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FIFO, LIFO Queues• First In First Out (FIFO)

– Initialize read and write pointers to first element

– Queue is EMPTY

– On write, increment write pointer

– If write almost catches read, Queue is FULL

– On read, increment read pointer

• Last In First Out (LIFO)– Also called a stack

– Use a single stack pointer for read and write