1 automated design of misaligned-carbon-nanotube-immune circuits nishant patil jie deng h.-s. philip...
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1
Automated Design of Misaligned-Carbon-Nanotube-Immune
Circuits
Nishant Patil
Jie Deng
H.-S. Philip Wong
Subhasish Mitra
Departments of Electrical Engineering & Computer ScienceStanford University
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Misaligned Carbon Nanotubes (CNTs)
Misaligned-CNT-Immune Logic Design
Aligned CNTs on Quartz – Prof. Zhou, USC
3
CNFET Transistor Layout
Substrate (e.g Quartz) CNT undoped region
Lithographic Gate
CNT doped region
Side View Top View
Oxide
CNT undoped region
4
Perfect CNFET Inverter Layout
V. Derycke et al., Nano Letters, p. 453, 2001.N+ doped
SemiconductingCNTs
Vdd Contact
OutputContact
Gnd Contact
Gate
Input
Input
P+ doped Semiconducting
CNTs64nm = 4λ
4nm
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CNFET Fabrication Process
Define cell regions on substrate
Etch CNTs outside cell regions
Define gates and contacts
Chemically dope CNTs
Vdd
Gnd
Out1 Out2
Gate A
Gate B
Gate B
Gate AGate
A
Gate B
GateA
Gate B
Out1 Out2
P+ doped CNTs
N+ doped CNTs
Vdd
Gnd
Undoped (intrinsic) CNTs
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CNFET Imperfections: Misaligned CNTs
Out
Gate A
Gate B
Gate A
Gate B
VddA
AB
Short
Vdd
Gnd
Gnd
OutB
Out
A B
C D
Wanted: AC + BD
Got: AC + BD + AD
Gnd
Vdd
Wanted: A+B in pullup; Got: Short
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BA
A
B
Misaligned-CNT-Immune NAND Design
Vdd
Gnd
Out
1. Grow CNTs
2. Define gates and contacts
3. Chemically dope P-type region
4. Chemically dope N-type region
5. Etch
Undoped region
enables misaligned-
CNT-immune design
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BA
A
B
Misaligned-CNT-Immune NAND Design
Vdd
Gnd
Out
1. Grow CNTs
2. Define gates and contacts
3. Etch CNTs
4. Chemically dope P-type region
5. Chemically dope N-type region
Etched region
enables misaligned-
CNT-immune design
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Generalized Algorithm
Characterize Layout
Misaligned-CNT-Immune
OR Misaligned-CNT-Vulnerable
Implement Arbitrary Logic function
Misaligned-CNT-Immune Layout
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Contact
Doped
Gate A
Gate B
Contact
CCC
GA GA
GB GB
D D D
D
D D D
D
DDD
Misaligned-CNT-Vulnerable NAND: Pull-up
A
B
Implemented FunctionA or B or
(A AND B) or 1 ==
1 != A or B
A
B
Contact
Contact
1
1
A
B
1
CCC
Path 1: C-D-A-D-C : fn = APath 2: C-D-B-D-C : fn = B
Path 3: C-D-A-D-B-D-C : fn = A & BPath 4: C-D-C : fn = 1
Intended Function A or B
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Misaligned-CNT-Immune NAND: Pull-up
UDGA GB
Doped
Doped
Gate B
Contact
Doped
Contact
Gate A
Doped
Undoped
Intended Function A or B
Implemented FunctionA or B or
(A and B) or (A and B and 0)
== A or B
B
Contact
Contact
A
Path 1: C-D-A-D-C : fn = APath 2: C-D-B-D-C : fn = B
Path 3: C-D-A-D-B-C : fn = A & BPath 4: C-D-B-UD-A-D-C : fn = 0
…
1
1A B
1
1
0
Contact
Contact
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Misaligned-CNT-Immune Arbitrary Function
Gates
A + (B + C)(D + E)Undoped regionsCNTs
CB
Vdd/ Gnd Contact
A
Output Contact
ED
Intermediate Contact
Immune to ANY number of misaligned CNTs Arbitrary logic function Formal correctness proof (Details in paper)
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Simulation Results
Penalties over Vulnerable CNFET Circuit
Cell Type Area Energy Delay [max {rise, fall}]
nand2 -1% 3% -7%
nand3 11% 15% 10%
nor2 -1% 5% 1%
nor3 11% 16% 10%
aoi21 -2% 1% 1%
Full Adder 12% 10% 7%
Misaligned-CNT-Immune vs. Misaligned-CNT-VulnerableCNFET model Deng & Wong, SISPAD 06
10% accuracy: DC & AC measurements Amlani, et al., IEDM 06
Significantly less penalty vs. traditional fault tolerance
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Conclusion
Misaligned CNT Immune Design
Perfect alignment not needed: immune by design
Ideal case: 13X better EDP vs. 32nm CMOS
Efficient misaligned-CNT-immune circuits
Significantly less overhead than replication
Metallic CNTs
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Thank You
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Misaligned-CNT-Vulnerable NAND: Pulldown
A
BGate B
Contact
Contact
Gate A
Doped
Doped
Doped
Intended Function A and B
Path: C-D-A-D-B-D-C
Implemented FunctionA and B
Contact
Doped
Gate A
Gate B
Contact
Doped
Doped
A
B
Contact
Contact
1
1
A
1
B
1
1
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