03/30/031 ece 551: digital system design & synthesis lecture set 9 9.1: constraints and timing...

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ECE 551: Digital System Design & Synthesis

Lecture Set 99.1: Constraints and Timing

9.2: Optimization(In separate file)

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ECE 551 - Digital System Design & Synthesis Lecture 9.1 - Constraints and Timing

OverviewConstraint ConceptsConstraint Classification

• Design Rule Constraints• Optimization Constraints• Defining timing paths and path delays• Setting Constraints

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Overview (continued)

Signal Interface Constraints• Drive characteristics for input ports• Load characteristics on output ports• Input delays and output delays

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Constraint Concepts

Constraints are used to:• Define limitations required for the target

technology to function properly• Specify the environment in which the design

must function in terms of input drive, output loading, temperature, power supply voltage, etc.

• Specify the design goals (other than functionality) in terms of bounds on input loading, output drive, area, performance, and power consumption.

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References

Design Compiler User Guide (DCUG)Design Compiler Reference Manual:

Constraints and Timing (DCRM)Design Compiler Reference Manual:

Optimization and Timing Analysis (DCRMO)

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Classification of Constraints

Design rule constraints• Implicit constraints defined by the

technology library• Required for the design to function

correctly• Apply to any design using the library

Optimization constraints• Explicit constraints defined by the user• Represent design goals

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Design ConstraintsFigure 1-1 RMCT (See Next Slide)Constraints:

• Maximum Transition Time• Maximum Fanout• Maximum and minimum capacitance• Cell degradation

Cannot remove default values from tech libCan make more restrictive than tech lib

values

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Maximum Transition Time

Maximum transition time for a net is the longest time required for its driving pin to change logical values. • Implies that slow transitions are to be

avoided. • What’s wrong with slow transitions?

Can be made more restrictive using set_max_transition

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Maximum FanoutPlaces fanout restrictions on driving pinsEach driven input or driven output port has a

fanout_load valueEach driving output has a max_fanout valueSum of driven fanout_loads must be no more

than max_fanout of driverFanout_load is dimensionless, typically a

value normalized to some unit capacitanceCan be made more restrictive by using

set_max_fanout and set_fanout_load

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Maximum and Minimum Capacitance

Permits limiting capacitance directly rather than implicitly using max_fanout and max_transition

Can make more restrictive by using set_max_capacitance

Similar for minimum capacitance which is more of a modeling constraint and has lower priority in terms of being met.

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Cell Degradation

Delays are often determined with an “ideal” input transition time on a cell

As the input transition time increases, delay increases for a given capacitive load increase

Cell degradation tables that list maximum capacitance that can be driven by a cell as a function of transition times at the inputs of a cell.

compile_fix_cell_degradation to fix table and set_cell_degradation to specify degradation.

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Precedence for Design Rule ConstraintsDefault higher priority than optimization

constraintsDescending order of priority

• Minimum capacitance*• Maximum transition• Maximum fanout• Maximum capacitance• Cell degradation

Try not to apply multiple constraints from list* Contradicts another statement in DCRM!

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Transition Time Calculation

CMOS delay model:• Transition Time = Drive R X Load C

Non-linear delay model:• Transition Time from table lookup and

interpolationSet_driving_cell and set_drive give

different behavior• If R-C model, same• If Nonlinear model,

set_driving_cell calculates transition time dynamically set_drive picks a value from midrange in table

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Design Rule Constraints Summary

set_max_fanout Input ports or designs

set_fanout_load Output portsset_load Ports or netsset_maximum_transition Ports or

designsset_cell_degradation Input portsset_min_capacitance Input ports

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Optimization Constraints

Timing constraints (performance & speed)• Timing paths• Constraint violations• Input and output delays (synchronous paths)• minimum and maximum delays

(asynchronous paths)Maximum area (# of gates)Minimum porosity (routability)

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Timing Paths

Timing path structure:

FFIN OUT

CLK

Primary inputto primaryoutput

Primary inputto register

Registerto register

Register toto primaryoutput

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Synchronous

Slack - the extra time available for signals to propagate from the clock to the input of a flip-flop (FF)

slack = clock period - path delay - setup

Constraint Violations

clock periodMaximum FF, combinationaland wiring delay

slack

setup

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Synchronous

“Hold” Slack - the extra delay present for signals to propagate from the clock to the input of a flip-flop (FF)

slack = path delay - clock period - hold

Constraint Violations (continued) CORRECTED

clock period

Minimum FF, combinationaland wiring delay

slack

hold

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Constraint Violations (continued)

Synchronous Timing Violations• Setup Time

Uses maximum path delay (worst case model)

Violation if slack < 0

• Hold Time Uses minimum path delay (best case model) Violation if slack < 0

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Constraint Violations

Asynchronous

Constraint Violation if• slack < 0

maximum delay

combinational andwiring delay

slack

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Constraint Violations

Asynchronous

Constraint Violation if• slack < 0

minimum delay

combinational andwiring delay

slack

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Clock, Input Delay and Output Delay

FFIN OUT

CLK

input_delay output_delay

CLK

CLK

The two clock signals are the same signal drawn to different scales.

Primary inputto primaryoutput

Primary inputto register

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Clocks, Input Delay and Output Delay (continued)

Examples:• create_clock -period 3.3 CLK

Establishes a clock CLK with period 3.3 ns

• create_clock -period 3.3 -waveform (10,25) \ -name SYS_CLK Establishes virtual clock for system without a clock

• set_input_delay 0.3 -clock CLK IN Value on IN is available 0.3 ns after CLK

• set_output_delay 1.0 -clock CLK OUT Value on OUT must be available 1.0 ns before CLK

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Maximum Delay and Minimum Delay

FFIN OUT

CLK

Primary inputto primaryoutput

max_delay

min_delay

Primary inputto register

max_delay

min_delay

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Maximum Delay and Minimum Delay (continued)

Examples:• set_maximum_delay 2.5 -from IN -to OUT

Specifies that the delay from IN to OUT is to be no more than 2.5 ns

• set_minimum_delay 1.0 -from IN -to OUT Specifies that the delay from IN to OUT is to be

no less than 1.0 ns

• set_maximum_delay 1.5 -from IN -to FF1/D

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Maximum Area

set_max_area area• Specifies the maximum allowable area

of the design in area units of the technology

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Minimum Porosity

Effective only for two-layer metal technology (therefore not used in our work)

set_min_porosity porosity [design list]• Specifies the part of the total cell area to

be used for over the cell routing• porosity - a percentage ratio of routing

track area over cells to cell area; from 0 to 90.