Dis t ribu t ion St a t e m e nt A – Approve d for Pub lic Re le a s e , Dis t r ibu t ion Unlim it e d

www.darpa.mil

De s ign & Se curit y: In t e llige n t De s ign of Ele c t ron ic s As s e t s (IDEA)

ALIGN: Analog Layout, Intelligently Generated from NetlistsSachin S. Sapatnekar1, Ramesh Harjani1 Jiang Hu2, Steven M. Burns3

1University of Minnesota, 2Texas A&M University, 3Intel

Automated no-human-in-the-loop netlist GDSIIOpen-source software targeting analog circuit layout for(1) Low-frequency ckts (2) Wireline (3) RF (4) Power delivery

Overview

30 years of analog layout automation research, little impactKey problem: design-specific solutions, no “theory of everything”• Rule-based methods find it hard to identify or encapsulate rules• Design cockpits act as designer assistants, without full automation

The ALIGN approach• Machine learning-driven recognition/annotation [key differentiator]• PDK abstraction on a regular grid, parameterized cell layout on grid• Block assembly under geometric and performance constraints

Background

2. PDK abstractionPitch, edge2edge constraints; Simplified design rulesApplied to multiple PDKs (FinFET + bulk tech.)

3.Cell generation: cell layout, parameterized by # fins, # transistors, C value, array size, presence of Vdd/gnd pin, etc.4. Place and route

Approach (continued)

Results: Auto-annotation using GCNs

Results

Key enablers for ALIGN to handle general circuits• Graph CNNs auto-annotate netlist blocks, constraints• PDKs abstracted to simplified grid-based systems• Automated parameterized cell layout for a primitive library

ɸ1

ɸ2

ɸ2 ɸ2

ɸ1 ɸ1

ɸ1

ɸ2

ɸ2 ɸ2

ɸ1 ɸ1

C2

C2

C3

C1

C1

C3

CA

C4

C4

CA

OTA

Ex. 2: Phased Array

These are all OTAs!

1. Auto-annotation: Represent circuit as a graphExact matching: Graph isomorphism for primitive blocks

Approximate matching

Graph CNNs (GCNs) used to recognize such higher-level blocks

Approach

vdd!

Vbp

Voutp

Voutn

Vinn

Vinp

n1

Vbn

gnd!

Id

M5

M4

M3

M2

M1

M0

vdd!

Vbp

Voutp

Voutn

Vinn

Vinp

n1

Vbn

gnd!

Id

M5

M4

M3

M2

M1

M0

GraphCurrent mirror

M0

100

010

M1001

S

D2

D1

S010

101M0 M1

D1 D2

Current mirror

M0

100

010

M1001

S

D2

D1

S010

101M0 M1

D1 D2

Vbp

Vinp Vinn

VoutpVoutnIdLoad

Current Mirror

Vbn n1

Vbp

Vinp Vinn

VoutpVoutnIdLoad

Current Mirror

Vbn

Differential OTACircuit

Training accuracy

minlengthmine2e

GCN

Hand-crafted OTA EqualizerDC-DC Conv.

Phased Array

…

Macro Placement

Full Placement

PlacementConstraints

Sim ula t e dAnne a ling

Analytical Placement,

Legalization

RoutingConstraints

…

Global Route

Detailed Route

Candidates Annotation

ILPSe le c t ion

Auto-annotation

Impact and Extensibility

Contact: Sachin Sapatnekar (sachin@umn.edu)Repo: https://github.com/ALIGN-analoglayout/ALIGN-public

SC Filter Layout

Parameterized Cells

Ex. 1: SC Filter

Identifying OTA nodes in a circuit

(and mixers, LNAs, …)

This research was developed with funding from theDefense Advanced Research Projects Agency(DARPA). The views, opinions and/or findingsexpressed are those of the author and should not beinterpreted as representing the official views orpolicies of the Department of Defense or the U.S.Government.