ALBA Digital LLRF

Angela SalomFrancis Perez

- RF & Diagnostics Section -

2/16ESLS-RF October, 2008

Outline

ALBA Overview

SR RF Plants parameters

Digital LLRF Conceptual Design

Hardware ModulesAnalog Front EndsTiming SystemsDigital board: Lyrtech

SoftwareLoops: Amplitude, phase and tuningDiagnostics

High Power tests results

Series Production of LLRF Crates

IFMIF-LLRF Prototype

3/16ESLS-RF October, 2008

ALBA Overview

ALBA is a 3rd generation synchrotron light source, located at 20 km from Barcelona, Spain.

Main parametersEnergy

3 GeVCircumference

268mBeam current

400mAEmittance

4 nm.radLifetime

≈10hRF Freq

500MHzBeamlines

7 at day 1

Picture August 08

4/16ESLS-RF October, 2008

Storage Ring RF Plants

6 RF Plants of 160kW at 500 MHz

2 IOT Transmitters per RF cavity. Power combined in CaCo

Dampy

CavityNormal ConductingSingle cell, HOM damped3.3 MΩ

Digital LLRF System based on IQ mod/demod

RF ParametersU0 1.3MeV/turnVtotal 3.6 MVq ≈

2.5fs ≈

9kHzPRF 960kW

5/16ESLS-RF October, 2008

Analog Front End

Down Conversion

FPGA

Digital IQ Demodulation

8DACs80MHz

Analog Front End

UpConversion

IOT2

RF Cavity Voltage (500MHz)

IF

RF Forward Cavity Voltage(500MHz)

Analog Timing System520MHz 500MHz

80MHz 80MHz

CAVITY

Tuning Control Loop

Digital Timing SystemPCI Bus

ICEPAPMotor Controller

13 RF Diagnostic Signals (500MHz)

IQ Ctrl IOT1& IOT2

IOT1CACO

DC

500MHz

8 ADCs80MHz

8 ADCs80MHz

FPGADigital IQ Demodulation

and Control Loops

Digital Timing System

Analog Front End

Down Conversion

FPGA

Digital IQ Demodulation

8DACs80MHz

Analog Front End

UpConversion

IOT2

RF Cavity Voltage (500MHz)

IF

RF Forward Cavity Voltage(500MHz)

Analog Timing System520MHz 500MHz

80MHz 80MHz

CAVITY

Tuning Control Loop

cPCI Bus

ICEPAPMotor Controller

13 RF Diagnostic Signals (500MHz)

IQ Ctrl IOT1& IOT2

IOT1CACO

DC

500MHz

8 ADCs80MHz

8 ADCs80MHz

FPGADigital IQ Demodulation

and Control Loops

Commercial Digital Board: cPCI

Analog Front End

Down Conversion

FPGA

Digital IQ Demodulation

8DACs80MHz

Analog Front End

UpConversion

IOT2

RF Cavity Voltage (500MHz)

IF

RF Forward Cavity Voltage(500MHz)

Analog Timing System520MHz 500MHz

80MHz 80MHz

CAVITY

Tuning Control Loop

Digital Timing SystemPCI Bus

ICEPAPMotor Controller

13 RF Diagnostic Signals (500MHz)

IQ Ctrl IOT1& IOT2

IOT1CACO

DC

500MHz

8 ADCs80MHz

8 ADCs80MHz

FPGADigital IQ Demodulation

and Control Loops

Analog Front End

Down Conversion

FPGA

Digital IQ Demodulation

8DACs80MHz

Analog Front End

UpConversion

IOT2

RF Cavity Voltage (500MHz)

IF

RF Forward Cavity Voltage(500MHz)

Analog Timing System520MHz 500MHz

80MHz 80MHz

CAVITY

Tuning Control Loop

Digital Timing SystemPCI Bus

ICEPAPMotor Controller

13 RF Diagnostic Signals (500MHz)

IQ Ctrl IOT1& IOT2

IOT1CACO

DC

500MHz

8 ADCs80MHz

8 ADCs80MHz

FPGADigital IQ Demodulation

and Control Loops

Control Inputs

Diagnostics Inputs

Digital LLRF Conceptual Design

Conceptual Design and Prototype

Digital Commercial Board: cPCI

with 16 ADCs, 8 DACs and Virtex-4 FPGA

Analog Front Ends for Downconversion (RF to IF) and Upconversion

(DC to RF)

Timing systems: 520MHz (500 + 20 MHz) for downconversion synchronized with digital 80MHz clock for digital acquisition

6/16ESLS-RF October, 2008

Front Ends and Timing System

Downconversion: From RF to IF

Timing Systems

Ref Signal (520 MHz) = MO + IFADCs Clock = 4*IFPhase shifter to adjust phase delay lines between RF plants

Upconversion: From DC to RF

IQ Modulator

DC I ControlDC Q Control

MO (500MHz)

RF Drive

VCXO (160MHz)

1/2

1/8

0/90º

IQ Mod

520MHz for Downconversion

Bandpass filter

Digital Timing System Analog Timing System

20MHz

80MHzCLK

10MHz

MO (500MHz)

7/16ESLS-RF October, 2008

FPGA Board

Lyrtech: VHS ADAC-4 cPCI

format

2 x 8 ADCs 125 MHz 14

bits

8 DACs 125MHz 14 bits

2 x Virtex

4

128 Mbytes RAM

8/16ESLS-RF October, 2008

Amplitude and Phase Control LoopsDigital IQ Demodulation PID Control Loop for IQ

Accumulator

+

-+

+

+

+

P action

Integral action

Set Point Kp

Input (I,Q)

Control Signal

Ki

error

SettingsDiagnostics

Step response in Close Loop (Cav&DACs)

0.95 1 1.05 1.1 1.15

x 10-3

30

40

50

60

70

80

90

100

t(s)

Cav

Sig

nals

(mV

)

ICavQCavCavAmpIRefCavRef

0.95 1 1.05 1.1 1.15 1.2

x 10-3

20

40

60

80

100

120

140

160

t(s)

DA

Cs

Out

put (

mV

)

IDACQDAC

Diagnostics signals of Loops

IQCav

IQ FwCav

Amplitude Fw

AmplitudeCav

Phase Fw Phase

IQ Error Control AmplitudeIQ Integral Action

Control PhaseIQ PID Output

9/16ESLS-RF October, 2008

Tuning LoopCordic Algorithm to calculate Cav – Fw phase differenceIterative process to calculate phase without employing any multipliersResolution better than 0.001º

after 16 iterations (1/80MHz * 16 = 0.2 µs)

Tuning Loop not always active to avoid plunger oscillations around 0ºphase

t=t0

∆φ

> 2º

Tuning Ont=t1

∆φ

= -1º

Tuning Offt=t2

∆φ

> 2º

Tuning

Ont=t3

∆φ

= -1º

Tuning

Offt=t4

∆φ

< -2º

Tuning Ont=t5

∆φ

= 1º

Tuning

Off

Phase measurements filtered at 2.4kHz rate to remove any noise.Resolutions achieved = 0.01º

10/16ESLS-RF October, 2008

Diagnostics

CavityCavity PowerForward and Reversed Cavity Power

Waveguide SystemFw

and Rv

Circulator InputFw

and Rv

Circulator OutputFw

and RV Load Power

Transmitter SignalsFw

Transmitter1 Input PowerFw

Transmitter2 Input PowerFw

and Rv

IOT-01 PowerFw

and Rv

IOT-02 Power

Slow Diagnostics: 1Hz rate (archiving)

Fast Diagnostics: Circular buffer of 128MBytes @ 80MHz (~ 50ms) Data retrieved after interlock happens or after user demand

Other RF signals Digital IQ Demodulated

11/16ESLS-RF October, 2008

Automated ConditioningAmplitude and duty cycle increase depending on vacuum levels

2 slow vacuum interlocks connected to LLRF

Cav

Vol

tage

t

Normal conditioning below vacuum limits

t

t

Vacc

um Vacuum Threshold 2

Vacuum Threshold 1

Conditioning with vacuum peaks above limits

Cav

Vol

tage

No vacuum peaksAdjustable amplitude slopeAdjustable duty cycle

Vacuum peaks above limitsAmplitude stops increasing when reaching upper vacuum limit, until vacuum comes back to lower limit

12/16ESLS-RF October, 2008

High Power testUp to 80 kW

y = 0.0004x2 - 0.0007xR2 = 1

0

10

20

30

40

50

60

70

80

90

0 50 100 150 200 250 300 350 400 450 500

IQ Drive [mV]

Pow

er [k

W]

Power Tests

Power tests at ALBA High Power RF Lab from 80w to 80kW

0 50 100 150 200 250

0

10

20

30

40

50

60

70

80

90

100

t(s)

mV

- D

egre

es

Reflected CavCav VoltFw Cav Volt

Amp & Ph loop OFFAmp & Ph loop ON -

Slow PIDAmp & Ph loop ON -

Fast PID

Dynamic

range: 30 dB

Loops performance:

Amplitude, Phase and

Tuning

loops

simultaneously

in operation

Close Loop

Open Loop

13/16ESLS-RF October, 2008

Amplitude and Phase loops

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10-4

433

433.5

434

434.5

435

435.5

436

436.5

437

437.5Cav Amplitude

t(s)

mV

Cav Volt 80MHzCav Volt 1MHzReference

Amplitude

RMS Errors:

δVrms

= 0.50mV/435mV = 0.11% @ 80MHz

δVrms

= 0.18mV/435mV = 0.03% @ 1MHz

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

x 10-4

44.75

44.8

44.85

44.9

44.95

45

45.05

45.1

45.15

45.2

45.25Ang Cav atan

t(s)

mV

Cav Phase 80MHzCav Phase 1MHz

Phase RMS Errors:

δPhrms

= 0.05º

@ 80MHz

δPhrms

= 0.02º @ 1MHz

Amplitude Resolution (75kW) Phase Resolution (75kW)

14/16ESLS-RF October, 2008

Tuning Loop

Cav-Fw

Phase

< 0.01º

@ 2.4kHz

Tuning Inputs filtering

Tuning Deadband

Cav Fw Dephase

0 10 20 30 40 50 60 70 800

10

48

586469

80

Pow

er (a

.u.)

0 10 20 30 40 50 60 70 80

-10

-3

-101

3

t(s)

Dep

hase

(Deg

rees

)

Cav VoltageReflected Power

Plunger Motion Plunger Motion

Tuning OnTuning Off

15/16ESLS-RF October, 2008

LLRF Crates Series Production

Crate Code # Mounted and tested

Loops Front End 7

Diagnostcis

Front Ends

15

Loops Patch Panel 8

Diagnostics Patch Panel

15

RF Distribution 7

Power Supply Units 8

Phase Shifters & Pin Diodes

8

RF Personal Safety System

8

Transmitter Patch Panel

6

MO Splitter 1

83 55/83

All components received from January – June 2008

Production started in July 200866% completely finished

10% in process

20% to be finished in October

LLRF racks pre-assembly starting in November 2008

16/16ESLS-RF October, 2008

IFMIF LLRF PrototypeCELLS and CIEMAT have signed and agreement to develop a LLRF prototype for

the accelerator IFMIF-EVEDA (International Fusion Materials Irradiation Facility -Engineering Validation Engineering Design Activities)

IFMIF: Future irradiation tool, aiming at qualifying advanced materials resistant toextreme conditions, specific to fusion reactorsthat will succeed to ITER

IFMIF-EVEDA: the construction of prototypes of the main units (prototype accelerator, lithium target and test cells)

IFMIF LLRF prototype

Based on ALBA Prototype (Lyrtech VHS-ADAC + Front module)Control loops of two RF chain per LLRF Fast Interlock Module integrated in LLRFRF Frequency 175MHz3 Kind of cavities: DTL, RFQ and SC HWR