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Analog Circuit Synthesis

enable Carrier-Grade QoS Services

advanced generation optimization© Copyright AgO Inc 20112

Agenda

• Company Background

• Challenges in Analog and RF design

• Overview of AnXplorer

• Competitive Differentiation


Company Background

• Focus on Analog & RF optimisation for improved production yield

• Founded by expert CAD developers in 2007• Previously in senior CAD development positions

at National Semiconductor– Strong track record 8 patent awards and 15 research

papers published

• AgO - Advanced Generation Optimization• Global Sales & Marketing Presence Q2 2010


Challenges in Analog & RF Design

Respin avoidance• Analog circuits are responsible for ~ 50% of IC design re-spins• Re-spins can mean missing market windows and unbudgeted costs

Achieving design specification• Meeting or beating performance while minimising cost of implementation• Managing greater complexity in operating and power saving modes

Maximising yield• Validating greater numbers of process, voltage and temperature corners• Efficiently centering design across all PVT corners

Design porting• Moving existing circuit designs to similar technologies• Re-centering design to meet constraints of new technology


Classic Analog Design Methodology• Design methodology has changed little over the years• Manual, iterative design with many SPICE runs

Define topology &

resize devices

Physical layout& adjust

ExtractionLayout verification

Designspecification &

constraints

Spice

Spice


AnXplorer Goals

• Quickly size and bias a circuit in a given technology

• Explore suitability of different design options for a given purpose in a short time

• Re-target designs from one process to another• Robust design in the face of process and

temperature variation• Support all types of devices

– Not limited to CMOS

• Give designer opportunity to explore results


AgO Design Methodology

AnXplorer automates device resizing using SPICE runs

Define topology

Physical layout& adjust

ExtractionLayout verification

Designspecification &

constraints

Feasibility analysis

Global optimization

AnXplorer

Centering


Porting of Existing Circuits

AnXplorer

Circuit intechnology X

Circuit sizedfor technology Y

Porting mode

Common challenge• Port existing design in technology X (say 180 nm) to technology Y (in 180 nm)• Ensure that original design goals are met

AnXplorer approach

• Start with original sized circuit• Define variable ranges for target circuit• “One click” command• Optimises and centers with new PVT

corners


Implicit Objectives

• Imposes implicit objectives on conditions of devices at DC operating point

• Customizable objectives• Detects common sub-circuits and

imposes constraints on their operating conditions

• Ensures a robust DC operating point

• Feature only available for MOS devices

Examples of sub-

circuits:

• transistors in

saturation• transistors in linear

region• current mirrors• level shifters• differential pairs• voltage reference• current mirror banks• etc


Hierarchical Design Objectives

• Most tools support a weight-based prioritisation for multiple objectives– Designer is often unsure of relative weights

• AnXplorer supports hierarchical design objectives– User defines relative priority of different objectives

• AnXplorer achieves more important objectives before optimizing others


Core Optimization Technology

Early Optimisation tools• Frequently relied on traditional convex/gradient methods• These are known to have difficulty with multiple local minima

AnXplorer• Based on Evolutionary algorithm• Capable of finding global minimum in presence of many local minima• Successfully optimised tough tests e.g. Rastrigin’s function• Optional logarithmic partitioning of design space

Supports both simulation-based optimization & equation-based optimization


Trade-off Analysis

• Finds multiple design points satisfying design objectives

• Creates exploration database for post-optimization analysis– Database stores all explored design points– Query language or GUI

• Useful for trade-off analysis with conflicting objectives

• Useful for “what-if” analysis


Industry Standard Formats

AnXplorer

Design objectives Un-sized circuit

Schematics

Sized and centerednet list

Exploration database for

Trade off analysis

Definition of Design variables

Compatible with existing design flows


Design Environment

• Spice Simulators– Cadence Spectre – Synopsys HSpice– Legend Design Technology MSim– Mentor Eldo – Silvaco SmartSpice

• Multi-threading support

• Operating system– Red Hat Enterprise Linux


Competitive Differentiation

• One product, four optimization strategies

• Robust centering to maximise yield

• Implicit objectives for stable DC operation (CMOS)

• Hierarchical design objectives

• User can perform trade-off analysis

• Industry standard formats and simulators

• Core based on Evolutionary Algorithm

• Solves tough optimization tests

• Performs better than traditional Gradient Algorithms


Promotion

• EE Times Global Coverage

• Document Download 300 per month

• No of customers engagement 50 in 2011

• Trade Show: DATE 2011 Grenoble France

ago-inc.com

AnXplorer New generation Analog & RF Circuit SynthesisDavid WoodDavid,[email protected] [email protected]@ago-inc.com

ago product overview

Technology

iterative design

design methodology anxplorer

existing design flows

multiple design points

design specification

original design goals

pvt corners design porting

design points query