a new computer vision processor chip design for automotive...

A new Computer Vision Processor Chip Design for automotive ADAS CNN applications

in 22nm FDSOI SOI Symposium Santa Clara, Apr. 13th, 2017

Dr. Jens Benndorf MD, COO Dream Chip

Dream Chip Technologies GmbH

Dream Chip Technologies

DCT Company Profile

Dream Chip Technologies …

• Positioned as a Fabless Microelectronic Engineering Company for medium to large SoC designs covering the whole range from Architecture, Specification, Design, Verification to GDSII

• Technologies: 130nm, 40nm, 28nm, 22nm FDX, 14/16nm FF

• 60 Employees/ 52 Engineers with 10 … 20 years SoC design experience

• Based in Hanover (HQ) and Hamburg, Germany

• Member of Silicon Saxony/ Germany

● Cadence Design Center Partner for Tensilica



Assisted Driving requires Cameras, Radar and Ultrasonic

Source: Texas Instruments



Use Case #1: Digital Mirroring

Source:



• Automotive multi camera systems for Bird-View, Rear-View and Panorama-View are a major part of today’s emerging technologies to make driving more safe and comfortable and to move towards autonomous vehicles.

Use Case #1: Digital Mirroring - The Multiview



Target Applications

• Automotive Camera-Monitor-Systems, e.g. electronic rear mirror

Key Features

• Works in YUV domain, independent of image sensor • Works on flicker frequencies from 80 Hz up • Unlimited flickering light sources in image • Optimized implementations available for several platforms, including

• Tensilica Vision P6 • TI TDA3 • nVidia CUDA • RTL (Q2 / 2017)

Use Case #1: Digital Mirroring – Flicker Mitigation



Use Case #2 : 360 deg Top View Camera



Use Case #3 : Pedestrian detection via CNNs



Partitioning of Algorithms



Introduction – Image Sensor Processing Overview



Heterogeneous Cores for Image Sensor Processing

GPU (VP6)

Vector DSP (VP6, HW)

A53

DSP (VP6, A53)



MPSoC Chip Architecture



I/O IF HEs: Pixel Level

Memory IF

Lock-Step A53: Object Level

Low Power CNN Architecture

VP6: Pixel Level



Floorplan

IVP: Pixel Level

Memory IF

Memory IF

Lock-Step

ARM A53: Object L.

• Tape-Out 10.Jan. 2017

• Global Foundries

– 22 FDX GF

– externally adjustable BIAS voltage

– 8x8 mm (64 mm^2)

• Calculation Power

– ARM Cortex A53 quad core

– 4x Tensilica Vision P6

– optimized for ADAS and CNN

– 4x video-in, 1x video-out

• MCM package

– DIE + 2x DDR4 on Silicon interposer



MPSoC Chip / Starter Kit



System in Package Design

System-on-Module features • 4GB LP-DDR4 3200 RAM Interfaces • Four 300MB/s video inputs • One 300MB/s video output • Gigabit Ethernet



Assembling the SOM...

Overview • Power management and

measurement • Chip power supplies included Benefits • Reduced application-specific

baseboard complexity • Interfaces customizable to

application requirements



Overview • DCT ADAS Quad-HDMI Base Board • Four HDMI 1.4b inputs • One HDMI 1.4 output • Custom high-speed headers available

Base board features • Video data rates up to 1080p60 • Two Intel MAX10 10M08DC FPGAs • Four high-speed interface headers • Video input synchronization • True output genlock possible

4 x HDMI Application Board



Demo



Mobile World Congress 2017 Demo



Thank You!

Please contact [email protected]


Steinriede 10 D-30827 Garbsen/Hannover

Germany +49-5131-90805-120

a new computer vision processor chip design for automotive...

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