a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014 2673

A Multiphase Buck Converter With aRotating Phase-Shedding Scheme For Efficient

Light-Load ControlYoungkook Ahn, Inho Jeon, and Jeongjin Roh, Senior Member, IEEE

Abstract—Mobile devices need to minimize their power con-sumption in order to maximize battery runtime, except duringshort extremely busy periods. This requirement makes dc-dcconverters usually operate in standby mode or under light-loadconditions. Therefore, implementation of an efficient regulationscheme under a light load is a key aspect of dc-dc converterdesign. This paper presents a multiphase buck converter with arotating phase-shedding scheme for efficient light-load control.The converter includes four phases operating in an interleavedmanner in order to supply high current with low output ripple.The multiphase converter implements a rotating phase-sheddingscheme to distribute the switching activity concentrated on asingle phase, resulting in a distribution of the aging effects amongthe phases instead of a single phase. The proposed multiphasebuck converter was fabricated using a 0.18 µm bipolar CMOSDMOS process. The supply voltage ranges from 2.7 V to 5 V, andthe maximum allowable output current is 4.5 A.

Index Terms—Efficient light-load control, multiphase dc-dc con-verter, PFM control, rotating phase shedding.

I. INTRODUCTION

T HE EMERGENCE of smart phones, tablet PCs, and otheradvanced devices has led to the rapid growth of the smart

mobile market. The performance of smart mobile devices de-pends entirely on their application processor (AP). Smart mo-bile devices are required to have significant processing powerin order to support their multiple functions. Since most smartdevices are operated with batteries, managing power consump-tion while meeting the requirements of each function has beenconsidered one of the most crucial issues in designing smart mo-bile devices. In the past, processing performance was improvedsimply by raising the clock speed. However, this approach putsconstraints on performance due to additional heat generationand power consumption. Multi-core processors have recentlyemerged due to advancements in very-large-scale integration

Manuscript received March 15, 2014; revised June 30, 2014 and September12, 2014; accepted September 20, 2014. Date of current version October 24,2014. This work was supported in part by the Ministry of Knowledge Economy,Korea, under the University ITRC support program supervised by the NationalIT Industry Promotion Agency (NIPA-2014-H0301-14-1007), and supported inpart by the Industrial Core Technology Development Program (10049095, “De-velopment of Fusion Power Management Platforms and Solutions for SmartConnected Devices”) funded by the Ministry of Trade, Industry and Energy.The authors are with the Department of Electrical Engineering, Hanyang Uni-

versity, Ansan 426-791, Korea (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2014.2360400

technology. Theses multi-core platforms are becoming domi-nant in providing sufficient processing power and flexibility tosmart mobile devices.A high-performance AP has a system-level power manage-

ment unit that efficiently manages power utilization and reducesunnecessary power consumption. Representative system-leveltechnologies include power gating and dynamic voltage and fre-quency scaling [1]. These technologies, which decrease unnec-essary leakage and dynamic power, are widely used for proces-sors that require high performance.The APs of smart mobile devices are required to have

high-performance dc-dc converters as well as system-levelpower management techniques in order to support high currentdensity and other stringent power constraints. The inductor-typeswitching dc-dc converters are widely and advantageously usedbecause of their high efficiency and high power capability.However, there are limitations in terms of current driving capa-bility and thermal management when only a single-phase dc-dcconverter is used for a high-performance AP. Comparison ofsingle-phase and multiphase dc-dc converters confirm that thelatter are beneficial due to higher current driving capability, asmaller output voltage ripple, a faster transient response, andimproved thermal management. Therefore, multiphase dc-dcconverters are good candidates for smart mobile devices thatrequire greater performance.Several advanced studies about multiphase dc-dc converters

have been conducted. The design and analysis of a fully inte-grated multiphase buck converter with on-chip filter inductorsand capacitors are presented in [2]. A high-frequency multi-phase hysteretic dc-dc converter using a delay-locked loop forautomatic synchronization of the remaining phases and elim-ination of external synchronization is reported in [3]. In [4],[5], a four-phase converter with off-chip air-core inductors onpackage is introduced. A highly integrated step-up multiphaseconverter with a high-voltage-tolerant digitally assisted con-troller is presented in [6]. A 100MHz four-phase fully integratedbuck converter equipped with standard package bondwire in-ductors and a flying capacitor topology for chip-area reductionis proposed in [7]. A pseudo-ramp current balance technique ispresented for a voltage-mode dual-phase buck converter in [8].A phase-shedding technique for adjusting the operational phasenumber according to the load current condition is introducedto enhance the light-load efficiency of high-power multiphaseconverters in [9]. A two-phase, four-segment dc-dc converteremploying phase-shedding/segmentation and a resonance gatedriver is proposed to improve light-load efficiency in [10].

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2674 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

Fig. 1. Average load profile of a typical smartphone.

Fig. 2. Conventional operation of the multiphase converter with phase shed-ding: (a) heavy load and (b) light load.

Fig. 1 shows a typical load profile of a smartphone [11].As shown in Fig. 1, the smart mobile device usually operatesin standby mode or under light-load conditions, except duringshort busy periods. Therefore, additional power managementis required to reduce unnecessary power consumption underlight-load conditions when a multiphase dc-dc converter is usedas a power management circuit for smart mobile devices. Thephase-shedding technique can help improve the efficiency ofmultiphase dc-dc converters over a wide load range [9], [10].The number of operating phases decreases when the load cur-rent is reduced, and a single phase will be connected eventuallyto the load system during a light-load condition. Inasmuch asmobile electronic devices usually operate in standby mode orunder light-load conditions, as shown in Fig. 1, the switchingstress of only one phase in the multiphase dc-dc converter in-creases compared to other phases, resulting in phase imbalanceand long-term reliability issues. This issue can cause degrada-tion in the system’s performance with respect to voltage ripple,current capability, and thermal dissipation, which are advan-tages of the multiphase converter topology.This paper presents a multiphase dc-dc converter for the

efficient light-load control and verifies its operation throughcircuit implementation and measurements. The converter hasfour phases for high current capability, and its output is stepped

Fig. 3. Block diagram of peak current control.

Fig. 4. Waveforms on the degradations of power transistors between PH0and the rest of the phases ( , , ,

F, nH, MHz).

down to a low voltage level. The converter also implementsboth pulse width modulation (PWM) and pulse frequency mod-ulation (PFM) for high efficiency in a wide load range. Thiswork proposes a rotating phase-shedding scheme for the distri-bution of the switching stress into all four phases instead of onlyone phase under light-load conditions. Section II explains theproposed rotating phase-shedding scheme. Section III presentsthe circuit details of the proposed multiphase converter. Themeasurement results are given in Section IV, and the conclusionis presented in Section V.

II. A MULTIPHASE BUCK CONVERTER WITH A ROTATINGPHASE-SHEDDING SCHEME

A. Reliability Issue of Previous Phase-Shedding Scheme

CMOS devices are affected by many reliability mechanismssuch as negative bias temperature instability (NBTI), hot car-

AHN et al.: A MULTIPHASE BUCK CONVERTER WITH A ROTATING PHASE-SHEDDING SCHEME FOR EFFICIENT LIGHT-LOAD CONTROL 2675

Fig. 5. Proposed rotating phase-shedding scheme under light-load conditions: (a) block diagram and (b) its waveforms.

Fig. 6. Simulation results of stress time versus PMOS threshold voltage in PH0: (a) a multiphase buck converter, (b) illustration of aging simulation, (c) agingcurves for , and (d) aging curves for ( F, nH, MHz).


rier injection (HCI), and time-dependent dielectric breakdown(TDDB) [12], [13]. The increased threshold voltage ofthe PMOS transistor is a common aging effect due to the ap-plied voltage stress [13]. Increased due to NBTI and HCIstresses in a switching dc-dc converter is directly related to theincreased on-resistance of the power transistors.Fig. 2 illustrates the conventional operation of a multiphase

converter with phase shedding under heavy- and light-load con-ditions. As explained in [9], [10], the phase-shedding techniquecanmaximize themultiphase converter’s efficiency by adjustingthe number of operating phases depending on the load current.Power is supplied to the output through the switching activity ofPH0 only at the light-load conditions as shown in Fig. 2(b). Theheavy use of PH0 can lead to acceleration of the aging effect onPH0 compared to other phases. The potential phase imbalanceand long-term reliability of the multiphase converter will resultfrom the heavy use of only one phase.The currentmode control has beenwidely used to designdc-dc

converters [14]. The basic current-mode controller and its vari-ations [15]–[18] can be used for the current sharing in multi-phase converters. The current-sensing circuit is a basic buildingblock of these controllers by the nature of the current-mode con-trol. Fig. 3 shows the block diagram of the peak current controlused in this work. A peak current mode control, which has theadvantages of a simple design and little effect on device param-eters, is one of the popular methods for current sharing amongthe phases [19]. The conventional phase-shedding scheme, how-ever, causes intensive stress and aging only on PH0 at the light-load condition. Since the aging effect introduces an increasedthreshold voltage of the transistor, the matching of each phase inthe multiphase converter will be destroyed by the heavy use ofthe single phase.The effect of themismatch is simulated inFig. 4.The increase in the threshold voltage from the aging effect couldbe as large as 100 mV or 200 mV for the heavily used phase, andFig. 4 shows the results of unbalanced inductor current from themismatch of each phase. The usual current sensing circuits [15],[16] have a sensing MOSFET in parallel with the PMOS powertransistor, and the sensingMOSFET is always in a deep triode re-gion, whichmeans that it always experiences high stress withoutrecovery time. Therefore, following a long aging effect on theheavily used phase, the current sensing accuracy also degrades.The large increase in the threshold voltage of the single switchingphase in the conventional phase-shedding scheme also impliesthe degradation of the power conversion efficiency. Therefore,the switching activity needs to be distributed for the phase bal-ance aswell as the long-term reliability ofmultiphase converters.

B. Proposed Rotating Phase-Shedding Scheme

Fig. 5 shows a conceptual block diagram of a rotatingphase-shedding scheme for distribution of switching activityunder light-load conditions. Balanced control of the phasesunder light-load conditions is achieved by rotating all phasesin sequence, which is possible by sequentially enabling onlyone phase, as shown in Fig. 5(b). When the converter beginsPFM operation under a light load, the controller selects oneswitching phase and shuts down the other three phases. Thissequential operation means that the proposed approach candistribute switching stress over all the phases for phase balance

Fig. 7. Efficiency degradation under PFM operation (atmV, mV, , and ).

without degrading the output voltage regulation characteristics.The main purpose of the proposed rotating phase-sheddingscheme is to distribute the aging effect of the transistors, so themismatch problem of the off-chip components cannot be alle-viated. The inductors and capacitors are off-chip components,and the proposed technique does not solve the mismatches fromthese off-chip components.Fig. 6 shows the comparison of the aging effects from the

conventional and proposed schemes. Both two-phase and four-phase converters are simulated. The MOSFET model reliabilityanalysis (MOSRA) tool in HSPICE [20] is used for aging anal-ysis of the power transistor. The PMOS threshold voltage is in-creased by the aging effect [12], and the aging effect is deter-mined by several factors such as the voltage conversion ratioand the load current. Since the voltage level across the inductordetermines the slope of the inductor current, the low inductorvoltage implies a longer PMOS turn-on time for the peak cur-rent controller in Fig. 3. This longer on-time of the PMOS tran-sistor means that the stress time will be longer than the recoverytime. More load current also implies that the switching periodin Fig. 5(b) becomes longer and the shutdown period becomesshorter. The transient time in the simulation indicates thecycle time for one rotation of all four phases. If load currentincreases, more switching activity at the PFM mode will berequired to supply the increased load current, and the rotationcycle of the four phases will become shorter, as shown in thesimulation. During the shutdown period, all power transistorsare turned off, and this recovery time alleviates the aging ef-fect. The threshold voltage of the PMOS transistor before agingis mV. When only single phase is switching, asin the conventional scheme, the variation of is aslarge as 230 mV through the period of five years as shown inFig. 6. The rotating phase shedding distributes the stress amongthe phases, and the is also equally distributed among thephases. The variation depends on the complex function of sev-eral factors for the aging and recovery effects [13], [20], and thefour-phase converter shows smaller than the two-phaseconverter. It can also be expected that the implementation ofmore than four phases will further reduce the variation.


Fig. 8. Block diagram of the four-phase dc-dc converter.

The largest variation of in Fig. 6 is used as a simulationcondition for Fig. 7. The difference of 76.8 mV in causesdifference in efficiency degradation under light-load conditions(PFM mode). The conventional scheme shows a maximum of2.5% decrease in efficiency due to the higher turn-on resistancecaused by the aging effect. The proposed scheme shows a max-imum of 0.86% decrease in efficiency by the distribution of theaging effect. Therefore, we can expect the mitigated light-loadefficiency degradation, as well as the balanced PWM operationthat was discussed in Fig. 4. If the load current is increased fur-ther, the operation mode changes to PWM mode and all phasesturn-on to supply large load current. The threshold voltages ofunused three phases in the conventional scheme increase lessthan those in the proposed distribution scheme, which impliesthat the overall conversion efficiency shows insignificant differ-ences at PWM mode.

III. CIRCUIT IMPLEMENTATION

A. Four-Phase dc-dc Buck Converter

Fig. 8 shows the proposed multiphase dc-dc buck converter,which includes four single-phase modulators that are controlled

in an interleaved manner. A peak current control is used forcurrent sharing among the phases [19]. Each phase in the pro-posed converter consists of power switches, a gate driver, a cur-rent-sensing circuit [16] for peak current control, and circuitsfor PWM/PFMmode operation. Each phase is controlled by en-able signals generated by the phase-rotation cir-cuit. The converter operates in PWM mode under a heavy loadcondition. Here, all phases are modulated with a phase differ-ence of 90 . The load located at the output is suppliedwith large currents through four inductors . and

are configured as off-chip resistors for easy control of theoutput voltage during the test. An error signal , which isthe difference between and , is applied equally toeach phase. The comparator located in PH0 generates a resetsignal by comparing to a summed signal . The restof the phases conduct the same action for generating reset sig-nals, but each has a phase difference of 90 . When the load cur-rent gradually decreases and the buck converter operates underlight-load conditions, the mode decision circuit changes the op-eration mode of the converter from PWM to PFM. Once themode is changed to PFM, the remaining phases, except oneactive phase, are disabled to reduce power loss. Unnecessary


Fig. 9. Block diagram of the PFM-mode buck converter.

blocks are also powered down during the PFM operation. Fromthis point, a single-phase buck converter regulates the outputvoltage. Unlike the conventional phase-shedding architecture,each phase in the proposed multiphase buck converter sequen-tially operates, using the phase-rotation control under a lightload. Therefore, the switching stress concentrated on PH0 canbe distributed over all the phases.

B. Control Circuits

With decreasing load current, the proposed multiphaseconverter automatically enters into PFM mode. The switchingactivity of the buck converter depends on the load currentcondition at PFM mode. Fig. 9 illustrates a simplified blockdiagram of a PFM-mode buck converter. When the multiphaseconverter operates in the pre-determined light-load state, thePWM/PFM detector converts the mode signal from high tolow after certain intervals determined by an internal counter.The PFM control monitors and regulates the output voltage;the monitoring includes both switching and shutdown periodsduring the PFM operation. When the converter enters theswitching period, the output voltage is controlled by peakcurrent control, which determines the reset timing of the SRlatch by comparing the sensing voltage to the peak currentthreshold, as shown in Fig. 9. The shutdown period beginswhen the output voltage rises above the high boundary voltage

. During the shutdown period, the PFM control turns offboth PMOS and NMOS power switches. The PFM controlcircuit in Fig. 9 generates the signal, which deter-mines the switching and shutdown periods. The repeat of theswitching and shutdown periods in PFM mode regulates thebuck converter’s output voltage within the boundary.

Fig. 10 shows the phase-rotation circuit and its corre-sponding waveforms. The proposed converter sequentiallytransmits to each phase using signalsgenerated by the phase-rotation circuit in Fig. 10(a). Therefore,each phase can share the switching period in sequence fordistributed switching activity, as shown in Fig. 10(b).Fig. 11 illustrates the circuit that generates clock signals re-

quired for the proposed four-phase buck converter. In the de-signed converter, each phase operates at a switching frequencyof 2 MHz. To make this possible, the four-phase clock gener-ator includes a clock generator that generates 8 MHz and digitallogics. The short pulse circuit in Fig. 11 generates the set clocksignal of 2 MHz, which is required for each phase of the mul-tiphase converter. During the shutdown period in PFM mode,the clock circuit is also powered down to minimize quiescentcurrent by using the signal from the circuit in Fig. 9.Differences usually occur in control mechanisms and hardwareimplementation of PWM controllers, especially depending onvoltage mode or current mode [14]. Each voltage mode or cur-rent mode also has slight variations in control hardware. How-ever, the PFM controllers usually have a relatively simple mech-anism, and Fig. 10 and Fig. 11 show most of the extra hardwareneeded to implement the rotating phase-shedding scheme.If the gate driver circuit for power switches is poorly designed

with a CMOS tapered buffer [21], a huge shoot-through cur-rent, which is an unwanted power loss in dc-dc converters, willflow through PMOS and NMOS power transistors during eachswitching transition. Therefore, a gate driver with dead-timedelay is needed to reduce shoot-though current loss. Fig. 12shows the gate driver circuit used in each phase of the pro-posed multiphase converter. Since the CMOS tapered buffer[21] would have series of large inverters, the switching noise


Fig. 10. (a) Phase-rotation circuit and (b) its corresponding waveforms.

Fig. 11. Four-phase clock generator.

and shoot-through current would be higher than the designedgate driver. In Fig. 12(a), when rises due to fast paththrough M1, also rises though the slow path of M1 and

M2. When falls due to the fast path through M4,also falls using the slow path through M3 and M4 as shownin Fig. 12(b). Here, the size of M2 and M3 can be adjusted to


Fig. 12. Gate driver circuit: (a) charging, (b) discharging, (c) dead-time control, and (d) simulation results.

Fig. 13. Layout and micrograph of a chip.

control the dead-time delays. Fig. 12(c) shows the dead-timecontrol circuit. The simulated waveforms of the gate driver aredisplayed in Fig. 12(d). The gate driving signals and

with dead-time delays are generated so that the PMOSand NMOS power transistors do not turn on simultaneously,avoiding a large shoot-through current.

IV. MEASUREMENT RESULTS

The multiphase dc-dc buck converter is designed and fabri-cated using a 0.18 bipolar CMOS DMOS (BCD) process.A buck converter includes four phases for high current capa-bility. For efficient light-load control, the proposed converteremploys the rotating phase-shedding scheme in PFM mode.Fig. 13 displays the layout and the micrograph of the proposed

Fig. 14. (a) Evaluation board and (b) cross-section of a QFN package on aPCB.

converter. The entire silicon area, including the bonding pads,is .Fig. 14 shows an evaluation board and the cross-section

of a quad-flat-no-leads (QFN) package on a printed circuitboard (PCB). The fabricated converter was packaged using aQFN package. As the converter can supply large currents toload circuits, thermal management is crucial for ensuring theconverter’s desired performance. The QFN package used forthe proposed converter includes a thermal pad at the center.Additionally, multiple thermal vias on the PCB are required forsmooth heat dissipation of the chip, as illustrated in Fig. 14(b).For easier achievement of a high-power supply and betterthermal management, a 1-oz board is used.The switching stress concentrated on PH0 under light-load

conditions, as shown in Fig. 2, is distributed by having eachphase in the proposed converter sequentially perform the


Fig. 15. Measured waveforms of SW nodes in PFM mode.

Fig. 16. Measured load regulation waveform.

switching activity using the rotating phase-shedding scheme.Fig. 15 displays the waveform of SW nodes in each phaseduring the operation of the proposed multiphase buck con-verter in PFM mode. The waveform shows that the switchingoperation of the proposed converter is not limited tounder a light-load condition but is distributed from to

by using the phase-rotation circuit in Fig. 10(a). Fig. 16shows the measured output voltage waveform of the converterwith respect to the variation in the load current; the load cur-rent varies between 150 mA and 3.7 A, with ,

, and MHz. The voltage waveformshows both PWM and PFM operations depending on

the load current level. The PFM operation has both switchingperiod and shutdown period, as shown in Fig. 10(b), and thewaveform in Fig. 16 clearly verifies these periods. The mea-sured waveform shows that the output voltage of the proposedconverter is well controlled under wide load current changes.Fig. 16 also shows that the applied rotating phase-sheddingscheme does not influence transient characteristics of theconverter.Table I outlines the performance of the fabricated chip. The

proposed converter has four phases to enable a high currentsupply and a dual mode (PWM/PFM) operation to improve the

TABLE ISUMMARY OF PERFORMANCE

light-load efficiency. The input voltage ranges from 2.7 V to 5V, and each phase operates at a switching frequency of 2 MHz.The maximum allowable output current is 4.5 A. The load reg-ulation is 4.83 mV/A at a load range of 0.3 A to 4.5 A. The lineregulation is 0.78 mV/V at a supply voltage variation of 2.3 V.Fig. 17 illustrates the measured power conversion efficiencies.For each conversion state, the peak efficiencies are measured as86.5% and 91.6%. The measurement results also show signifi-cant improvement of efficiencies by using the PFM operation inthe light load conditions.This work and prior studies are compared in Table II. All

dc-dc converters presented in [3], [5], [7], [8], [10] werefabricated using CMOS processes. Most studies use highswitching frequencies for LC filter size reduction and a fastresponse, and have comparable output current capabilities.Hysteretic, unlatched PWM, and voltage-mode (VM) controltechniques are used for output regulations. Moreover, multi-phase topologies are used for high current driving capabilityand low output voltage ripples. In [7], [10], phase-sheddingschemes are used to improve light-load efficiencies. In [8], theswitching frequency of 600 kHz is used for each phase andmaximum load current is 2 A. The proposed current-mode(CM) converter includes four phases and can provide a highoutput current of 4.5 A. The converter has a single batteryvoltage range and high efficiency, over 90%. Unlike otherstudies, this work includes both PWM and PFM controls forhigh efficiency in a wide load range and implements a rotatingphase-shedding scheme for phase balance and long-term relia-bility of the multiphase converter.

V. CONCLUSION

This paper presents a multiphase CM buck converter for APsthat require high current at low battery voltage. The proposedconverter includes four phases that enable a high current ca-pability, and it has a dual mode function to increase heavy-and light-load efficiencies. The controller implements a rotatingphase-shedding scheme to alleviate a potential phase imbalanceissue caused by concentrated switching stress on one phase onlyunder light-load conditions. The switching stress is distributedby having each phase sequentially perform a switching activity


Fig. 17. Measured efficiencies: (a) , , (b) , .

TABLE IIPERFORMANCE COMPARISON OF INTEGRATED MULTIPHASE BUCK CONVERTERS

in PFM mode. The functionality of the proposed converter witha rotating phase-shedding scheme is verified through circuit im-plementation and measurement results.

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Youngkook Ahn received the B.S. degree inelectronic and electrical engineering science,Kyeongsang National University, Jinjoo, Korea,in 2006. He received the M.S and Ph.D. degreesin electrical engineering and computer science,Hanyang University, Ansan, Korea, in 2009 and2014, respectively.He is now with Dongbu-Hitek, Seoul, Korea, as

a Senior Researcher, where he has been involved inthe Smart Power IC Design Part. His research inter-ests include power management circuits and mixed-

signal integrated circuits.

Inho Jeon received the B.S. and M.S. degrees inelectronics and communication engineering fromHanyang University, Ansan, Korea, in 2012 and2014, respectively. He is currently working towardsthe Ph.D. degree in the same university. His cur-rent research interests include power managementcircuits and mixed-signal integrated circuits.

Jeongjin Roh (M’01–SM’10) received the B.Sdegree in electrical engineering from HanyangUniversity, Seoul, Korea, in 1990, the M.S. degreein electrical engineering from the Pennsylvania StateUniversity, State College, PA, USA, in 1998, andthe Ph.D. degree in computer engineering from theUniversity of Texas at Austin, TX, USA, in 2001.From 1990 to 1996, he was with Samsung Elec-

tronics, Kiheung, Korea, as a Senior Circuit Designerfor mixed-signal products. From 2000 to 2001, hewas with Intel Corporation, Austin, Texas, as a Se-

nior Analog Designer for delta-sigma data converters. In 2001, he joined thefaculty of Hanyang University, Ansan, Korea. His research interests includepower management circuits and oversampled delta-sigma converters.

a multiphase buck converter with a rotating phase-shedding scheme for efficient light-load control

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