a hybrid architecture for radar processing

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A Hybrid Architecture for Radar Processing Jack West, Hongping Li, Sirirut Vanichayobon, Seok-Hyun Ko, Jeff Muehring, John Antonio, Sudarshan Dhall University of Oklahoma DARPA Contract No. F30602-97-2-0297 SAR Processing Flow STAP Processing Flow Range Compression Doppler Filtering Weight Computation Range Compression Azimuth Processing Data Transfer Data Transfer Data Transfer Azimuth Range Range Doppler Channel FFT Size Azimuth Sectioned Convolutions Kernel Size Section Overlap PCI MOTHER BOARD PENTIUM DRAM WILD ONE SRAM SRAM ANNAPOLIS WILDFORCE ANNAPOLIS WILDFORCE ANNAPOLIS WILDFORCE ANNAPOLIS WILDFORCE HARD DISK DRIVE Physical View of Prototype System Data Source VME Mercury System CN CN PE PE . . . . . . SPARC Reconfigurable Subsystem DSP/GPP Subsystem Dat a Sin k Annapolis System 120 MB/sec PC 120 MB/sec 120 MB/sec PC PCI Custom Custom PE PE . . . Reconfigurable Subsystem Annapolis System PCI 120 MB/sec CN CN CN CN CN CN CN CN CN CN CN CN CN CN DRAM ASIC RIN-T VME BACKPLANE MERCURY RACE MCH 9U BOARD HARD DISK DRIVE D R A M SPARC ROUT-T FORCE SPARC 5V CN PCI MOTHER BOARD PENTIUM DRAM WILD ONE SRAM SRAM ANNAPOLIS WILDFORCE ANNAPOLIS WILDFORCE ANNAPOLIS WILDFORCE ANNAPOLIS WILDFORCE HARD DISK DRIVE Architecture of Prototype System

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SPARC. ANNAPOLIS WILDFORCE. ANNAPOLIS WILDFORCE. ANNAPOLIS WILDFORCE. ANNAPOLIS WILDFORCE. VME. Annapolis System. Annapolis System. Mercury System. PCI. PCI. Custom. Custom. PC. PC. PE. PE. PE. PE. CN. CN. Data Source. Data Sink. Reconfigurable Subsystem. - PowerPoint PPT Presentation

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Page 1: A Hybrid Architecture for Radar Processing

A Hybrid Architecture for Radar ProcessingJack West, Hongping Li, Sirirut Vanichayobon, Seok-Hyun Ko, Jeff Muehring, John Antonio, Sudarshan Dhall

University of OklahomaDARPA Contract No. F30602-97-2-0297

SAR Processing Flow STAP Processing Flow

RangeCompression

DopplerFiltering

WeightComputation

RangeCompression

AzimuthProcessing

DataTransfer

DataTransfer

DataTransfer

Azimuth

Range

Range

Doppler

Cha

nnel

FFT Size

Azimuth Sectioned Convolutions

KernelSize

Section

Overlap

PCI MOTHER BOARD

PENTIUM DRAM

WIL

D

ON

E

SR

AM

SR

AM

AN

NA

PO

LIS

WIL

DF

OR

CE

AN

NA

PO

LIS

WIL

DF

OR

CE

AN

NA

PO

LIS

WIL

DF

OR

CE

AN

NA

PO

LIS

WIL

DF

OR

CE

HARD DISK DRIVE

Physical View of Prototype System

Data Source

VME

MercurySystem

CNCNPEPE... ...

SPARC

ReconfigurableSubsystem

DSP/GPPSubsystem

Data Sink

AnnapolisSystem 120 MB/sec

PC

120 MB/sec120 MB/sec

PC

PCI Custom Custom

PEPE...

ReconfigurableSubsystem

AnnapolisSystem

PCI

120 MB/sec

CN

CN C

N

CN

CN C

N CN

CN

CN

CN

CN C

N CN

CN

DR

AM

AS

IC

RIN

-T

VME BACKPLANE

ME

RC

UR

Y R

AC

E M

CH

9U

BO

AR

D

HA

RD

DIS

K D

RIV

E

DR

AM

SP

AR

C

RO

UT

-T FO

RC

E S

PA

RC

5V

CN PCI MOTHER BOARD

PENTIUM DRAM

WIL

D

ON

E

SR

AM

SR

AM

AN

NA

PO

LIS

WIL

DF

OR

CE

AN

NA

PO

LIS

WIL

DF

OR

CE

AN

NA

PO

LIS

WIL

DF

OR

CE

AN

NA

PO

LIS

WIL

DF

OR

CE

HARD DISK DRIVE

Architecture of Prototype System