A Digital PFC Controller withoutInput Voltage Sensing

Barry Mather, Bhaskar Ramachandran and Dragan MaksimovicColorado Power Electronics Center, ECE Department, University of Colorado, Boulder, CO 80309-0425

Barry.Mather, Bhaskar.Ramachandran, Dragan.Maksimovic I @colorado.edu

Abstract- This paper introduces a novel digital PFC (DPFC)control approach that requires no input voltage sensing orcurrent loop compensation, yet results in low-harmonic operationover a universal input voltage range and loads ranging fromhigh-power operation in continuous conduction mode down tonear-zero load. The controller is based on low-resolution DPWMand A/D converters, requires no microcontroller or DSPprogramming, and is well suited for a simple, low-costintegrated-circuit realization, or as an HDL core suitable forintegration with other power control functions. Experimentalverification results are shown for a 500 W boost PFC rectifier.

LINTRODUCTION

Power factor correction (PFC) boost rectifiers are used in awide range of applications that are required to meet theEN61000-3-2 standard. At low-to-medium power levels, thetransition-mode control (i.e. critical conduction mode, oroperation at the boundary of continuous conduction mode(CCM) and discontinuous conduction mode (DCM)), whichoffers simplicity and performance advantages, is widely usedand supported by a range of commercially available low-costcontrollers. At higher power levels (above several hundredWatts), CCM operation is often preferred because of lowerconduction losses and reduced EMI filtering requirements.Averaged current mode control in combination with a slowvoltage control loop and a multiplier, which is a well-knowncontrol approach for CCM PFC, requires a more compleximplementation compared to the transition-mode control. Withthe motivation of simplicity comparable to transition-mode orDCM operation, together with low-harmonic, low conductionloss, and low EMI performance in CCM, the nonlinear-carrier(NLC) control technique was introduced in [1, 2]. Thistechnique eliminated the needs for input voltage sensing,current loop compensation, and a precision analog multiplier.Variations in the implementation of the analog NLC controlapproach have been reported in [3-6], and are now used incommercially available controllers [7, 8].

Digital PFC controllers, offering improved system interface,power management features, support for multi-moduleoperation, and improved voltage-loop dynamic responses,have recently received increased attention. Most of the digitalPFC control techniques reported so far have been based onDSP or microcontroller implementations (e.g. [9-19]), or haverelied on multiple current samples per switching period[20, 21].

L i(t)

Fig. 1: DPFC controlled boost rectifier

The purpose of this paper is to introduce a novel digital PFC(DPFC) control approach based on a simple current controllaw that allows operation in CCM without input voltagesensing. Further objectives are to show how low-harmonicoperation over a universal input voltage range and a widerange in power can be achieved using low-resolution A/Dconverters, a low-resolution digital pulse-width modulator(DPWM) and minimal digital hardware. Figure 1 shows ablock diagram of the boost converter with the proposed DPFCcontroller.The paper is organized as follows: Section II introduces the

DPFC current control law. Section III describes the voltageregulation loop and addresses mitigation of limit-cyclingoscillations related to quantization of power. Section IVdiscusses system implementation, quantization issues andexperimental results for a 500W boost DPFC rectifier.Conclusions are given in Section V.

II. DIGITAL PFC CURRENT CONTROL LAW

With reference to Fig. 1, in a PFC rectifier the currentcontrol objective can be written as: ig= VgIRe, where vg is therectified line voltage, ig is the low-frequency (average)component of the inductor current, and Re is the emulatedresistance, Re = Vg,rmIs2P (P is the input power) [22]. Using thequasi-static relationship for the CCM boost converter,VOU(P-d) = vg, where d is the switch duty ratio, the currentcontrol objective can be expressed as

(1)

where

1-4244-0714-1/07/$20.00 C 2007 IEEE.

(I d) Voutp (I ) = -(1-d)9 R 2 ue V., rms

198

2 R= grms =- e

VoutP VOut(2)

takes the role of a power control signal. In analog NLCapproaches [1, 2], (1) is solved using a voltage comparator byconstructing a carrier waveform based on d -X t/T,. A differentapproach, better suited for digital realization follows bysolving (1) for the duty cycle command d[n] directly as afunction of the current sample i[n]=ig[n], where i[n] representsa sample of the inductor current ideally in the middle of theswitch on time or in the middle of switch off time, and u is thepower control signal:

d[n] = 1- uig [n] = 1- ui[n] (3)

Equation (3) is the basic version of the proposed DPFCcurrent control law. Note that (3) requires no input voltagesensing or compensation in the current control loop. Figure 2shows experimental waveforms illustrating operation of aDPFC controller based on (3). The current A/D conversionstart (CONVST) and end of conversion (EOC) signals showhow the inductor current is sampled in the middle of theswitch off time (as in [18, 23]) and the duty cycle commandd[n] is then updated based on the current sample. A triangle-wave DPWM facilitates current sampling in the middle of theswitch off time (or in the middle of the switch on time).A. Stability ofthe current control loop

In this section, we examine small-signal stability of thecurrent control law (3) starting from a discrete-time modelbased on the quasi-static approximation, i.e., assuming that theinput voltage Vg and the output voltage Vou, can be consideredconstant on the time scale of several switching periods T,From the large-signal relationship [23],

i[n + 1] = i[n] + g T - out (1- d[n])T(4)

a small-signal discrete-time relation yields the control-to-current transfer function:

Gid(Z) -V 0 Ts (5)d() L z-1

Linearization of (3) gives the effective current-loopcompensator transfer function:

Gic(z)= d(z) -u (6)i (z)

Combining (2), (5) and (6), we obtain the effective discrete-time current control loop gain,

3-.

4-.

...............OOV ..Ch2 .CONVh T-..... ...... ........ ..... ....10VUoSW- CH2 5.006 V Bw M 2.00p's Ch3fijI 2.2 v

Ch3 5.00 v w Ch4 5.00 V w

Fig. 2: Experimental waveforms illustrating operation of theboost PFC based on the DPFC current control law (3)

RT 1 1

T(z=Gd(z)Gi,(z)= L2K1critz I(7)

where Kcrit = ReTJI2L is a parameter that determines theoperating mode (CCM or DCM) of the boost converter in thePFC rectifier [22]. Based on (7), stability of the current controlloop can be examined using root locus with Kcrit as a gainparameter, as shown in Fig. 3(a). The root locus shows that thecurrent loop is stable (i.e. has a pole inside the unit circle) aslong as Kcrit < 1, which is the same condition that characterizesthe PFC boost operating in CCM over the entire line cycle[22]. In conclusion, the current loop based on (3) is small-signal stable at high power levels when the converter alwaysoperates in CCM. At lower power levels, the boost converteroperates in DCM around the zero crossings of the ac line, andin CCM around the peak of the ac line. Instability of thecurrent loop in such CCM operation typically manifests itselfas current period-doubling, which may be tolerated. It isnevertheless of interest to investigate modifications of thecurrent control law to achieve stable operation in CCM atlighter loads, i.e. for larger values of Kcrit. In particular, weconsidered a control law based on a weighted sum of twocurrent samples,

d[n] 1-uig[n] =1-u( i[n]+(1-a)i[n-1]) (8)

The maximum stable Kcrit value is attained when cx = 0.75.The corresponding root locus shown in Fig. 3(b) indicatescurrent loop stability for Kcrit < 2. This effectively extends therange of stable operation from Kcrit < 1 to Kcrit < 2, or down tohalf of the power level at which the converter starts operating

Fig. 3a. Fig 3b.199 Fig. 3: Root-locus of T(z) for (3a) the current control law given in (3),

and (3b) the current control law in (8) for cx = 0.75

I

in DCM for a portion of the line period than previously. Ateven lighter loads, the converter is in DCM most of the time.B. Operation at light loadsAt very light loads the converter will operate in DCM duringthe entire input voltage line cycle. To maintain voltageregulation in light load conditions a further modification isadded to the current control law,

d[n] = dmax -u (a i[n] + (1- a)i[n -1]) (9)At light loads, the power control command u saturates at Umaxwhich is set based on stability criteria. Beyond this point,further reductions in power are accomplished by reducing themaximum duty cycle, dmax. At higher power, when u < umax,dmax is equal to 1, thus reducing the control law (9) back to (8)(or (3)). This modification makes voltage regulation possibledown to essentially zero load even for high input voltagelevels, at the expense of somewhat increased current distortionat such light loads.

III. VOLTAGE REGULATION AND POWER CONTROL

A block diagram of the boost rectifier with the completeDPFC controller is shown in Fig. 4. Based on the sampledoutput voltage error, the voltage loop controller G, computesthe power control signal u[n]. As described in the previoussection, as the power is reduced, the command u saturates atUmax = 0.5 for (3). Control through dmax then enables powercontrol down to zero load.

Figure 5 shows a small-signal model of the power stageobtained by averaging over half line cycle [22], for the DPFCcurrent control law described in Section II. This model is usedto design a standard slow voltage loop control where G, canbe a simple linear PI compensator. To remove the need forsynchronization to the ac line, and to facilitate extensions of

d

l l fii[n] ~~~~~~~~~~~~~Voltage-loopl..

~~~~~~~~compensator .d- DPFC Umx en

S ~~~~CDurrFent T9 7 \), CCn Control Law Umin|

I 1 Digital PFC Controller V

Fig. 4: Complete DPFC controller. Experimental prototype parameters: universalinput voltage range, V0 = 380V, L = lmH, C = 230uF, transistor: FCP2ON60,

diode: 15ETX06, switching frequency: lOOkHz, maximum power: 500W

the proposed DPFC controller to fast voltage control (as in [18]or [19]), we sample the output voltage at the switchingfrequencyf, which is much higher than the line frequencyfine.The large oversampling ratio fJfi,, is also very beneficial in

resolving an issue related to power quantization. Averagepower delivered to the load is determined by the value of thepower command u. In the interest of minimizing the hardwarerequirements, it is beneficial to reduce the word size for thepower command. However, at high power levels the powerdifferential between a 1 LSB step in u may becomeconsiderably large; meaning that the resolution of powerlevels drops significantly compared to lower power levels.The quantization of u, however, means that the powerdelivered to the load may not match exactly the powerconsumed by the load. As a result, the voltage loop enters alow-frequency limit-cycling mode (subharmonic with respectto the line frequency) leading to highly undesirable operationfor a PFC. As an example, Fig. 6(a) reveals low frequencyoscillation near the apex of the current waveform.

Next, let us consider how the power quantization problemcan be completely resolved in the DPFC controller. First,notice that the small-signal model in Fig. 5 includes an outputresistance equal to one half of the small-signal load resistance.As a result, even in the case of an ideal power sink load (anideal downstream DC-DC regulator), there is a finite small-signal resistance loading the output, which helps stabilize theoutput voltage at zero average error even with finite powerresolution of the controller. Second, given the largeoversampling ratio fJfjine, XA modulation can be very effectivein improving effective resolution of the power command u,with minimal hardware overhead. This is even more so indigital PFC controllers than in digital controllers for DC-DCconverters where effective XA techniques were previouslydescribed [24].

In the DPFC realization, we implemented a simple, first-order XA modulator (XAu in Fig. 4) in the "error-feedback"configuration [25], as shown in Fig. 7. The command withword length of ni, bits is effectively reduced to a ditheredcommand with word length of n0u, < ni, bits. In theexperimental prototype, for u dithering, we have ni, = 16,nout= 8. The result of u dithering can be observed in Fig. 6(b)for the same operating conditions as in Fig. 6(a). In theexperimental results of Section IV we further show how udithering through XA modulation removes undesirablesubharmonic limit-cycling under all operating conditions.

g2vg,rmsf j2U4 r2 C R \

P2 V2J2-v2 ;r2 2P

g ,rms

Fig. 5: Averaged small signal model of the DPFC controlledboost for slow voltage loop design

200

Chi 100 v. . 5.00 MgM2.OOms Ch2f 6OOmVFig. 6a.: no SA dithering implemented

Vg..

.. .. .. ..

............. .......................... ........

.. .. .. .. ..

.. .. .. .. .. .. g.

Chi 100V S.OOVV M2.00ms Ch2f 6.lmVFig. 6b: YA dithering only

..... ..,.. .. ...

Vg

... ...

... .. .... ... ....

....... ..

........................... ......................

.. .. ..

Cnh uuv 5.0uuV v2i.0uums OuumvFig. 6c: u and d SA dithering

Fig. 6: Converter waveforms for various SA dithering settings, P500W, Vg rws = 120 Vrms, 4-bit DPWM, 8-bit current sensing ADC

IV. SYSTEM IMPLEMENTATION

The experimental prototype consists of a boost rectifierpower stage and a digital controller implemented using aXilinx FPGA development platform. The digital controllerallows experimentation with the resolutions of current sensing(up to 8-bit, 33 mA current LSB resolution), voltage sensing(up to 8-bit, 3 V LSB output voltage resolution), and the

Vg = 120 Vrms Vg = 220 Vrms

(bits) mA/bit THD (%) THD (%)8 33 4.3 2.37 65 4.4 2.46 130 4.7 2.75 260 5.3 3.54 521 6.1 5.43 1042 8.1 9.1

Table 1: THD measurements for various current ADC resolutions, 4-bit DPWM,P= 500W

resolutions of the DPWM and the current sensing ADC wereinvestigated to this aim.

i. DPWM resolution

The resolution of the DPWM was variable from 1-bit to 9-bits. During experimentation it was determined that the 1-bitand 2-bit settings were simply not feasible and representedextreme quantization effects. Implementing a first-order LAmodulator (YA d in Fig. 4) to dither the duty-cycle comand dallowed the DPWM resolution to be lowered to as low as 3-bits while maintaining harmonic limit standards at a 500Wpower level. A DPWM setting of 4-bits, with YA modulationimplemented, was found to be a suitable setting for theoperation of the boost PFC over the entire range of inputvoltages and output power levels.

ii. Current sensing ADC resolution

The current sensing ADC had a variable resolution of 3-bitsto 8-bits. Table 1 shows how changing the current senseresolution effects the total harmonic distortion (THD) of theline current. The current sensing resolution in mA/bit is alsopresented in Table 1. For this experiment the DPWMresolution was set to 4-bits of resolution and YA modulationwas enabled for both the u and d signals. The current LSBquantization step is as high as 1 A in the case of a 3-bit currentsense A/D, however, at 500W the harmonic current limits arenot exceeded.

iii. Combined quantization effects

Figure 9 shows three line current waveforms for differentYA modulation implementations. Real-time inspection of thecurrent waveform shown in Fig. 8a reveals low frequencyoscillation near the apex of the current waveform. Circleshave been added to show the locations of the oscillations thatlead to the aforementioned undesirable sub-harmonics.Figure 8b shows the current waveform when IA, isimplemented, the sub-harmonic steps are no longer present buta stair-step appearance still is present in the current waveform.With YAd and YA, implemented, Fig. 8c produces a cleanwaveform that easily meets harmonic current specifications.Figure 9 is a plot of the harmonic currents for the sameconditions as shown in Fig. 8. Harmonic current values areshown for both the YAd and YA, enabled and IA, only settings.

201

:: ~~~Vg

..a

*k

Current ADC Resolution

Fig. 7: Error-feedback configuration of a first-order YAmodulator for dithering

The Class A harmonic current limits for the odd harmonics arealso shown. Without YAd active the 3-bit DPWM is notcapable of passing the harmonic current limits, with YA denabled the 3-bit DPWMV easily passes the harmonic currentlimits. A total of six internal dithering bits (LSBs) wereutilized for the 3-bit DPWMV setting.

B. Experimental waveforms

i. Operation at high and moderate power

Table 2 shows the experimental line current (ia3, therectified line voltage (vg) and the output voltage ripple (vrippie)waveforms for different line voltages (220 Vrms and 120 Vrms)and loads (500 W and 100 W) with a 4-bit DPWM and a 4-bitcurrent sensing ADC. The Class A harmonic current limitsare mieet fur all operating conditions.

I1-+I

ii. Operation at very low power

Figure 10 shows the converter waveforms at a line voltageof 220 Vrms and a load of 20 W. The converter output is stillregulated and the line current meets harmonic currentstandards although the THD is compromnised.

V. CONCLUSIONS

This paper introduced a novel digital PFC (DPFC) controlapproach that requires no input voltage sensing or current loopcompensation, yet results in stable, low-harmonic operationover a universal input voltage range and load ranging fromhigh-load operation in continuous conduction mode down tonear-zero load. The controller architecture, together withsimple, first-order IA modulation blocks for control signaldithering, enable DPFC controller realization with a low-resolution DPWM, low resolution A/D converters, and a lowclock rate. The DPFC controller is suitable for stand-alonelow-cost custom-IC implementation, or as a Verilog HDL(hardware description language) module well suited forintegration with other power control functions. Experimentalverification results are shown for a 500W boost DPFCrectifier.

14-+

Fig. 8a.: no YA dithering implemented

Chi: 10''' .... S.OOVQ2 M2.OOms Ch2\-c 2.3 VFig. 8b: YA, dithering only

.Chi' bOYv 5.00 VQ M2.00ms 'Chf2\-V 2.3 VFig. 8c: u and d YA dithering

Fig. 8: Converter waveforms for various YA dithering settings, P=

500W, Vgrn

u dithering only

~u and d dithering

odd harmonic limits

3 7 1 1 15 19 23 27 1 35 39Hamoi Number

Fig. 9: Harmonic currents with and without XA d dithering implemented, P500W, Vg, 120 Vrm,s, 3-bit DPWM, 4-bit current sensing ADC

Fig. 10: Converter waveforms for very light load

operation, P =20W, Vg, =220 Vrm,s, 4-bit DPWMand current sensing ADC

Vg,rms =l12OVrmst

--.

'ac

Vripple

Chll 100 V 5.UU VS M2.OUms 1h12 'L uumvam 10.0V%\

1 -+

KE

3-+

1 -+

3-'

chii bO v M 2.OOYSI M42.OOms Ch2X- SSOm Y,Ch3 IO.O0V"%

Table 2: Experimental waveforms for 100W and 500W for input voltages of 12OVm, and 220Vm,

203

0.6-

0.5-

r

1.E

c

m

Vg,rms = 220 Vrms

P= IOOW

P = 500W

Vripple

I

RE

CflI uu0V ME 2.00UVS iM2.uums Lf2 52umVCh3 2.SO0V"%

Lfl I IUUV ~~~~~~f .UU .Vivtu m Lfl .m..Ch3 2.SO0V%l

,pple

Vg

.a

.r

,. F. . -.' k k ... .FS. OWL. -. 'kk I I- . . I 11 11 L. -; -. F. A I I I 11 I I

I

1.1- . .'.k 1. " ..- - - -- 11- ..- ',..-A '-' - -I

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