7-segment displays digilent spartan 3 board discussion d3.3

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7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

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Page 1: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

7-Segment Displays

Digilent Spartan 3 Board

Discussion D3.3

Page 2: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

Spartan 3 Board

Page 3: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

Spartan 3 Board

Page 4: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

Turning on an LEDNote: A zero turns on the LED

+3.3VR

FPGA output pin1

+1.6V

No current

Currentlight

R =voltagecurrent =

1.5

15 x 10-3 = 100 ohms

LED

no light+3.3V

+3.3VR

FPGA output pin0

LED

+0.1V

Page 5: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

Spartan 3 Board

Page 6: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

7-Segment Decoder

a

b

c

d

e

f

g

dp

a b c d e f g dp

q0

q1

q2

q3

seg7dec

a-g LOW to turn on segment

Page 7: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

7-Segment Display

q a b c d e f g0 1 1 1 1 1 1 01 0 1 1 0 0 0 02 1 1 0 1 1 0 13 1 1 1 1 0 0 14 0 1 1 0 0 1 15 1 0 1 1 0 1 16 1 0 1 1 1 1 17 1 1 1 0 0 0 0

a

b

c

d

e

f g

a

b

c

d

e

f g

q a b c d e f g8 1 1 1 1 1 1 19 1 1 1 1 0 1 1A 1 1 1 0 1 1 1b 0 0 1 1 1 1 1C 1 0 0 1 1 1 0d 0 1 1 1 1 0 1E 1 0 0 1 1 1 1F 1 0 0 0 1 1 1

Truth tableseg7decq(3:0) AtoG(6:0)

Page 8: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

library IEEE;use IEEE.std_logic_1164.all; entity seg7dec is port (q: in STD_LOGIC_VECTOR(3 downto 0);

AtoG: out STD_LOGIC_VECTOR(6 downto 0));end seg7dec;

7-Segment Decoder

seg7decq(3:0) AtoG(6:0)

Page 9: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

architecture seg7dec_arch of seg7dec isbegin process(q) begin case q is when "0000" => AtoG <= "0000001"; when "0001" => AtoG <= "1001111"; when "0010" => AtoG <= "0010010"; when "0011" => AtoG <= "0000110"; when "0100" => AtoG <= "1001100"; when "0101" => AtoG <= "0100100"; when "0110" => AtoG <= "0100000"; when "0111" => AtoG <= "0001101"; when "1000" => AtoG <= "0000000"; when "1001" => AtoG <= "0000100"; when "1010" => AtoG <= "0001000"; when "1011" => AtoG <= "1100000"; when "1100" => AtoG <= "0110001"; when "1101" => AtoG <= "1000010"; when "1110" => AtoG <= "0110000"; when others => AtoG <= "0111000"; end case; end process;end seg7dec_arch;

Page 10: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

-- seg7decwith q select

AtoG <= "1001111" when "0001", --1"0010010" when "0010", --2"0000110" when "0011", --3"1001100" when "0100", --4"0100100" when "0101", --5"0100000" when "0110", --6"0001111" when "0111", --7"0000000" when "1000", --8"0000100" when "1001", --9"0001000" when "1010", --A"1100000" when "1011", --b"0110001" when "1100", --C"1000010" when "1101", --d"0110000" when "1110", --E"0111000" when "1111", --F"0000001" when others; --0

7-Segment Display

a

b

c

d

e

f g

a

b

c

d

e

f g

Behavior(Active LOW)

VHDL

AtoG

seg7decq(3:0) AtoG(6:0)

Page 11: 7-Segment Displays Digilent Spartan 3 Board Discussion D3.3

NET "AN<0>" LOC = "E13" ;NET "AN<1>" LOC = "F14" ;NET "AN<2>" LOC = "G14" ;NET "AN<3>" LOC = "d14" ;NET "AtoG<6>" LOC = "E14" ;NET "AtoG<5>" LOC = "G13" ;NET "AtoG<4>" LOC = "N15" ;NET "AtoG<3>" LOC = "P15" ;NET "AtoG<2>" LOC = "R16" ;NET "AtoG<1>" LOC = "F13" ;NET "AtoG<0>" LOC = "N16" ;NET "dp" LOC = "P16" ;

.ucf file