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Delay-Fault Testing Tutorial

Acknowledgement: This presentation is adapted from

Professor Janak Patels tutorial on the same topic available

on the web at:http://courses.ece.uiuc.edu/ece543/docs/DelayFault_6_per_page.pdf

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Delay Fault Testing Tutorial 2

Outline

Common Fault Models (Review)

Defects and Delay Faults

Delay Fault Models Transition Faults

Path Delay Faults

Robust Path Test Non-robust Path Test

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Common Fault Models

Fault Model De inition

Stuck-at Fault (S F) Logic line stuck at 0 or 1

(can be single or multiple)

Bridging Signals x and y become

D(x,y) or (x,y)

Stuck-open Signal x stuck in some

previous state

Delay n I/ path bet een clocked

elements has excessive delayCoupling Signals x and y become F(x,y)

attern Inter erence Signals interact in space & time

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Only if no other path delay is increased.

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Exercise

Consider the 4-Nand implementation of the

XOR gate in the previous slide. There are

six I/O paths hence 12 path delay faults. For

each of these faults, determine if it isrobustly testable, only non-robustly testable

or not testable (functionally redundant).

Provide justification for your answers.

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Broadside is also called launch-off-capture test.Skewed-Load is also called launch-off-shift test.

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Timing forlaunch-off-captureTransition-delay

fault testing

IC: Initialization ClockLC: Launch Clock

CC: Capture ClockSEN: Scan Enable

This figure is borrowed from the paper, Ahmed et al., ITC-2005, Paper 11.1

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Timing forlaunch-off-shiftTransition-delay

fault testing

IC: Initialization ClockLC: Launch Clock

CC: Capture ClockSEN: Scan Enable

This figure is borrowed from the paper, Ahmed et al., ITC-2005, Paper 11.1

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Delay Fault Testing Tutorial 34(See Prof. Patels website for details on SegmentTest)

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