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Page 1 從2D SOC 到 3D IC Dec. 11, 2009 by Jing Jou Tang /STC-ITRI 唐經洲

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  • Page 1

    2D SOC 3D IC

    Dec. 11, 2009

    by Jing Jou Tang /STC-ITRI

  • Page 2

    Moore (1965)

    Number of Computer per Integrated CircuitRel

    ativ

    eM

    anuf

    actu

    ring

    cost

    per

    Com

    pute

    r

    2008/04 in Golden Moores Office

  • Page 3

    Skyscrapers

    Location : TaiwanHeight : 508 MFloors : 101Built : 2004

    Location : DubaiHeight : 705 MetersFloors : 160To Be Completed : 2008

    Location : MalaysiaHeight : 452 MetersFloors : 88Built : 1998

  • Page 4

    2D vs. 3D

    http://www.jonathassociates.com/AJA/droppedImage.png

    20(TSV)

  • Page 5

    2D vs. 3D

  • Page 6

    Via First Process

    Source: Yole

    Source: IBM SEMATECHIMEC

  • Page 7

    Via Last Process

    Wet EtchingPlasma (DRIE) Etching

    Laser drillingSource: Fraunhofer IZM

    [email protected] XIL ALCATEL

    Source: Yole

    Source: SEMITOOL

  • Page 8

    3D Integration

    Source: NXP

  • Page 9

    Why Not SOC ?

    (Cost) (Material) (Lithography) 3D (Transistor Architecture) (Variability) (Thermal Dissipation)

  • Page 10

    Limitation of SiP

    Limited BandwidthLimited DensityLimited PerformanceLimited Capability of Mass Production

  • Page 11

    Possible Future Application

    Mobile Graphic IC+ CPU + MemoryCPU+ MemoryGPU+ MemoryLED Driver: RAM+VGAHeterogeneous MemoryLCD Driver+ luminance Sensor + LED

    Driver

  • Page 12

    Tezzaron 3D Memory Devices

  • Page 13

    NEC 8DRAM

  • Page 14

    SamsungTSVDDR3 (1/3)

  • Page 15

    (Koyanagi)DRAM

  • Page 16

    Elpida 3D DDR3 DRAM Source: http://www.elpida.com/en/news/2009/08-27.html

    Roadmap: 8G TSV DRAM/Sample (before the end of 2009 )16G TSV DRAM (mid 2010)

  • Page 17

    Samsung 3D IC NAND Flash

    Samsung 16Gb NAND stack with TSV

    http://www.techpowerup.com/10837/Samsung_Develops_3D_Memory_Package.html

  • Page 18

    IMEC 3D IC Memory

  • Page 19

    Matrix (Sandisk) 3D Memory

    OTP (One Time Programmable)Architecture

    Hybrid Scaling Segmented Word line architecture2001/2003TSMC 0.25um CMOS

  • Page 20

    Booming Factors/Time of 3D IC

    202020192018201720162015201420132012201120102009~2008

    Power

    Performance

    Form Factor

    Time to Mkt.

    Cost

    Heterogeneous

    CISMemory

    CISMemory

    CISMemory

    CPU

    CISMemory

    CPU

    CISMemory

    CPURF/MEMS

  • Page 21

    Join Us

  • Page 22

    3D IC/

    AdAd--STACSTAC(())

    EDA

    SIPO

    /

    : FablessFabOSAT:

  • Page 23

    More Closed Link on 3D IC

    CMP

  • Page 24


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