28 june 2004 atlas sct/pixel tim fdr/prr martin postranecky: ttcrm/ttcrq1 atlas sct/pixel tim...

28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq 1

ATLAS SCT/Pixel TIM FDR/PRR28 June 2004

Physics & AstronomyHEP Electronics

Martin PostraneckyJohn Lane, Matthew Warren

TTCrm versus TTCrq


TTCrm• Originally selected as the TTCrx

mezzanine board to be used on TIM-3• Uses 2 connectors J1 and J2• Just fits on single-width board

But last year reported :• Potential Phase Shift of the clock output

of up to 400 ps, depending on the activity on the commands channel B

• Potential increased clock jitter up to 150-200ps RMS on the TTCrm clock outputs


TTCrq

• Additional QPLL reduces this potential jitter from TTCrx chip to about 50 ps peak-to-peak

• QPLL has narrow locking range of +/- 3.7 kHz around 40.0786 MHz ( < +/-100 ppm )

• TTCrq board requires one additional connector J3 for the QPLL inputs/outputs ( in addition to the J1 & J2 )

• 7mm tall spacers on all connectors required for backward compatibility with TTCrm

Ref : http://ttc.web.cern.ch/TTC/TTCrqSpec.pdf http://proj-qpll.web.cern.ch/proj-qpll/images/manualTTCrq.pdf


TTCrm TTCrq

J1 ( below ) J2 ( below ) J2 ( top ) J1 ( top )

J3 ( top ) TTCrm versus TTCrq


TTCrm versus TTCrq TTCrx and QPLL Mezzanine Card (TTCrq)

Paulo Moreira, Ernest M u rer – 12/02/2003 Rev 0.1 – Preliminary

In trodu ct ionA new me zzanine ca rd is bein g de sig ned as an al terna tive to the exis ting TT Crm sup por te dby the CERN Elec tronics Pool (EP-ESS Group). The aim is twof old: to produc e a card thatcan be mou nted on a standard V M E uni t without imposi ng res trictions o n t he spaci ngbe twe en two m odule s an d to add the QP LL fun ctionali ty to the boa rd 1 . Ad ditionally the Tr ue Ligh tpin -prea mp (T RR -1B 43 -000 ) w ill replace the A gilen t (HFB R – 2316 ).T he new TT Crx m ezzani ne card will be backward- compatible with the TT Crm. That m eanstha t the exis ting elec trical connec tors (J1 an d J2 ) will be k ep t in the s ame ph ys ical po s itionswi th t he sam e pinou t. A n addi tional co nne ctor (J3) will be adde d t o t he ca rd loca ted on t hePCB side o pposite to the o ptical conn ect o r si de as rep resented in Fi gure 1. J3 will be a 26-pi ncon nec tor. (V ME board a reas u nde r the dotted/ sh adowed re gion s (top view d rawi ng) sho uldremain free for tool in se rtion du ring board re moval .)

2.54 mm

2.54 mm

55.88 mm

60.96 mm

66 mm

60.96 mm66 mm

48.3 mm

8.3 mm

2.5 mmJ1 J2

2.54 mm

15.24 mm 30.48 mm 15.24 mm

12 1212

TrueLightTRR-1B43-000

31.75 mm 29.21 mm

27.94 mm 25.40 mm

2.54 mm

(Top view)


TTCrm versus TTCrq

• A new mezzanine card is being designed as an alternative to the existing TTCrm supported by the CERN Electronics Pool (EP-ESS Group). The aim is twofold: to produce a card that can be mounted on a standard VME unit without imposing restrictions on the spacing between two modules and to add the QPLL functionality to the board1. Additionally the TrueLight pin-preamp (TRR-1B43-000) will replace the Agilent (HFBR – 2316).

• The new TTCrx mezzanine card will be backward-compatible with the TTCrm. That means that the existing electrical connectors (J1 and J2) will be kept in the same physical positions with the same pinout. An additional connector (J3) will be added to the card located on the PCB side opposite to the optical connector side as represented in Figure 1. J3 will be a 26-pin connector. (VME board areas under the dotted/shadowed regions (top view drawing) should remain free for tool insertion during board removal.)

TTCrm versus TTCrq


TTCrm versus TTCrq


• Up to 400 ps peak-to-peak on CLOCK40DES1 output pin J1 pin 2

• Phase shift of clock seen when running with continuous L1A triggers

NOTE : Jitter on CLOCK40DES1 on J1 pin 2, triggering on the raising edge of clock,

at about +1V trigger threshold, and about 10 usec ( = 400 clocks ) from trigger point

Scope set to infinite persistence

TTCrm CLOCK JITTER OBSERVED :


TTCrm Clock Jitter

CLOCK40DES1

Trig. not running

200pS/divDelay 10uSJitter ~ 400pS p-p


TTCrm Clock Jitter

CLOCK40DES1

Trigger running

4.0nS/divDelay 10uSClock Phase Shift


TTCrm Clock Jitter

CLOCK40DES1

Trigger running

200pS/divDelay 10uSJitter ~400pS p-pClock Phase Shift


TTCrq CLOCK JITTER OBSERVED :

• Up to 200 ps peak-to-peak on CLOCK40DES1 output pin ( with QPLL selected and locked )

• When running with continuous L1A triggers, the QPLL looses lock repeatedly ( about once every 15 triggers received )

• NOTE : The TTCrq module used in these tests was an untested sample on loan to UCL.

Our clock runs at 40.08 MHz, which should be

inside the locking range


TTCrq Clock Jitter

CLOCK40DES1

500pS/div

Delay 10uSec

Jitter ~ 200pS p-p


TTCrq – Jitter on Backplane

PCLKB output

500pS/div

Delay = 10uSec

Jitter ~ 300pS p-p


Clock Delay

CLOCK40DES1

PCLKB

Delay ~ 8nS


CONCLUSION :

• TIM-3B modified so that it will accept and run with either TTCrm or TTCrq.

• All additional inputs and outputs on TTCrq connector J3 are connected to FPGA-2 to allow control and use of QPLL if required

• Extra 7mm tall spacers required on all TTCrq connector pins for backward compatibility to TTCrm

28 june 2004 atlas sct/pixel tim fdr/prr martin postranecky: ttcrm/ttcrq1 atlas sct/pixel tim...

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