14. Memory testingMotivation for testing memories (4)Modeling memory chips (6)Reduced functional fault models (17)Traditional tests (7)March tests (7) Pseudorandom memory tests (10)

1.1 Importance of memoriesMemories dominate chip area (94% of chip area in 2014)Memories are most defect sensitive partsBecause they are fabricated with minimal feature widthsMemories have a large impact on total chip DPM level Therefore high quality tests required(Self) Repair becoming standard for larger memories (> 1 Mbit)% of chip areayear

Memory%

201654

521632

711316

8398

9084

9442

Memory

Logic-Reused

Logic-New

Sheet1

MemoryLogic-ReusedLogic-New

99201654

02521632

05711316

088398

119084

1494042

Sheet2

Sheet3

1.2 Memory chip cost over time

Dollars per DRAM chipPrice of high-volume parts is constant in time; except for inflationNote: Slope of line matches inflation!

1.3 Table with test times

Note: A memory is tested with several algorithms, which together may go through the total address space over 100 times Effective test time for 16 Mb DRAM, using O(n) tests, is about 168 s Test time reduced using on-chip parallelism (DFT and BIST)

n

Number of bits

Algorithm complexity (Cycle time = 150 ns)

O(n)

O(n*log2n)

O(n3/2)

O(n2)

1 K

0.0001 s

0.001 s

0.003 s

0.1 s

1 M

0.1 s

2.1 s

110 s

30.6 h

4 M

0.42 s

9.2 s

860 s

20.3 d

16 M

1.68 s

40.3 s

1.91 h

325 d

64 M

6.71 s

174 s

15.3 h

14.2 y

256 M

26.8 s

2.09 h

122 h

228 y

1 G

107 s

8.94 h

977 h

3655 y

1.4 Problems with testing memoriesNumber of bits/chip increases exponentially (4*in

2.1 Functional SRAM memory model

Fig. 4.2 pag. 35

2.2 Electrical SRAM cell modelStructure of a CMOS SRAM cell (left cell below)Q1--Q3 and Q2--Q4 form inverters (Q3 and Q4 are the load devices)Inverters are cross coupled to form a latchQ5 and Q6 are pass transistorsAddressing of a cell usesa row address (using the word line WL)a column address (using the bit lines BL and BL*)OperationsWrite: precharge BLs; drive BL, BL* and WLRead: precharge BLs; drive WL; feed BLs to sense amplifiers

SRAMCell withPolysiliconLoad DevicesL1 and L2

2.3 Electrical DRAM cell modelDRAM cell stores information as a charge in a capacitorCell capacitance 40 fF = 40* 10-15 F; BL capacitance 300 fF!(SRAM cell stores information in terms of the state of a latch)This charge leaks away over timeDRAMs require refresh circuitry (Refresh rate: 64 ms)DRAM cells require 1/4th the area of SRAM cellsDRAM cells dissipate less power (thicker gate oxide)DRAMs are less sensitive to Soft ErrorsDRAMs are slowerOperationsRead: precharge BL; drive WL; feed BL to sense amplifierWrite: drive BL; drive WL

2.4 DecodersDecoders address a specific cell in the Memory Cell Array MCAIf the MCA would be a vector, then 1 Mbit MCA requires 1M WLsBy arranging the cells in the MCA in a two-dimensional structure,a 1 Mbit MCA requires 1K WLs and 1 K BLsThis is a significant reduction in the decoder area!Hence, the MCA is two dimensional and consists of rows and columnsThe Column decoder selects a particular ColumnThe Row decoder selects a particular RowDecoders may be simple logic gate structures Example of a simple k-input decoder

2.5 Read/write driversThe write driver can be rather simpleThe data-to-be-written is presented on BLThe inverse data-to-be-written is presented on BL*

The sense amplifier can be a simple inverter; e.g. for small arrays, which have strong signalsa differential amplifier; for larger arrays, which have weak signals

2.6 The reduced functional modelFor test purposes Functional model reduced (simplified) to three blocks The functional faults also reduced:single-cell faults (SAFs, TFs, etc.)two-cell faults (Coupling faults)k-cell faults (NPSFs)The functional fault models havea hierarchy:1. Stuck-at fault (SAF)2. Transition fault (TF)3a. Coupling fault (CF)3b. Neighborhood pattern sensitive fault (NPSF)

3.1 Notation for describing faults describes a fault describes a single-cell faultS describes the state/operation sensitizing the faultA fault is sensitized when the fault effect is made presentF describes the fault effect in the victim cell (v-cell) describes a two-cell fault (a Coupling Fault)S describes the state/operation of the aggressor cell (a-cell) sensitizing the faultF describes the fault effect in the v-cellExamples: a SA0 fault : a SA1 fault: an TF : a TF: a CFid: a CFid: a CFid : a CFid1-cell fault 2-cell fault /;

3.2 Stuck-At Fault (SAF)The logic value of a Stuck-At cell or line is always: 0: a SA0 fault1: a SA1 faultOnly one fault (a SA0 or a SA1) can be present at a time

SAF fault type has two subtypes

3.3 Stuck-Open Fault (SOpF)SOpF: A cell cannot be accessed; e.g., due to an open in its WLWhen a read operation is applied to a cell, the differential sense amplifier has to sense a voltage difference between BL and BL*In case of an SOpF BL and BL* have the same (high) levelOutput Sense Amplifier:fixed value (SOpF behaves as a SAF)previous value of sense amplifier Detected when in a march element a 0 and 1 is read. Required form of the march element: (,rx,,rx*)3. random (fault detected probabilistically)Every read operation detects the SOpF with a probability of 50%

3.4 Transition fault (TF)A cell fails to undergo the following transition(s):Fails up-transition: a TFFails down-transition: a TFFault type has two subtypes: the and the TFA single cell may contain both faultsThe Set input may not work (e.g., SA0)The Reset input may not workTest: Every cell should make and transition and be readDefectConceptual TF representation

3.5 Data retention fault (DRF)DRF: A cell cannot retain its logic valueTypically caused by a broken pull-up device which causes the leakage current of the node with a logic 1 not to be replenishedAfter a time delay Del (Typically: 100 ms Del 500 ms) the cell will flipThe DRF fault type has two subtypes, which may be present simultaneously in the same cell: and means that a logic 1 will become a logic 0 after a delay time T

3.6 Faults involving 2 cells: Coupling Faults CFsCF: The state of, or an operation applied to, the a-cell (aggressor cell) forces or changes the state of the v-cell (victim cell) Fault type Idempotent CF: CFidA transition write operation (=0 1 & =10 change) applied to the a-cell forces the contents of the v-cellCFid has 4 subtypes: , , and The or write operations to a-cell sensitize the faultThe 0 or 1 are the fault effect in the v-cellIn addition, each subtype has two positions: A. address of a-cell < address of v-cellB. address of a-cell > address of v-cell

3.7 Coupling faults (CFst, CFin)State CF (CFst): A CF whereby the state of the a-cell forces a fixed value in the v-cellFour fault subtypes : , , and Each subtype has 2 positions: addr. a-cell < addr. v-celladdr. a-cell > addr. v-cellInversion CF (CFin): A transition write operation to the a-cell toggles the contents of the v-cell (Note: denotes toggling)Two fault subtypes exist: and Each subtype has 2 positions: addr. a-cell > addr. v-celladdr. a-cell < addr. v-cellNote: CFin not a realistic faultAn SRAM cell is a latch, rather then a flip-flop Cannot toggle!

3.8 Pattern sensitive fault (k-CF, PSF)A k-Coupling Fault (k-CF), also called a Pattern Sensitive Fault (PSF), involves k cells which form a neighbourhoodThe v-cell is also called the base cellThe k-1 non-v-cells are the deleted neighbourhood cellsThe k cells can be anywhere in memoryExample: Active PSF A CFid with k-2 enabling valuesa = a-cell, v = v-cell, e = enabling cell

Neighbourhood PSFs (NPSFs) more realisticThe cells have to be physical neighbours Example: Active NPSF (ANPSF)a-cell sensitises fault in v-celliff e-cells have enabling statePSFNPSF

3.9 Pattern sensitive fault (NPSFs)A Neighbourhood PSF (NPSF) is a restricted k-CFThe deleted neighbourhood cells have to be physically adjacent to the base cell

Active NPSF (ANPSF): A conditional CFidA CFid requiring the k-2 e-cells to have to have an enabling state

Passive NPSF (PNPSF): A conditional TFA TF requiring the k-1 e-cells have to have an enabling state

Static NPSF (SNPSF): A conditional CFstA CFst whereby the k-2 e-cells have to have an enabling stateCFstTF

3.10 Validation of the fault modelsPerformed by (Dekker, ITC88) for SRAMs8 K*8 = 64 Kbits, 4 Transistor (4T) cellstechnology: 4 m (Note: R-defect is defect resistivity)Distribution for R-defect values assumed to be uniformi.e., no FAB statistics taken into account

Table shows likelihood of functional faults, as a function of the spot defect sizeResults: Two new fault models established: SOpF and DRFSAFs 50%CFs due to large spot defectsCFin not present!

Functionalfault class

Spot defect size (m)

3.11 March tests: Concept and notationA march test consists of a sequence of march elementsA march element consists of a sequence of operations applied to every cell, in either one of two address orders:1. Increasing () address order; from cell 0 to cell n-12. Decreasing () address order; from cell n-1 to cell 0Note: The address order may be any sequence of addresses (e.g., 5,2,0,1,3,4,6,7), provided that the address order is the exact reverse sequence (i.e, 7,6,4,3,1,0,2,5)

Example: MATS+ {(w0);(r0,w1);(r1,w0)}Test consists of 3 march elements: M0, M1 and M2The address order of M0 is irrelevant (Denoted by symbol )M0: (w0) means for i = 0 to n-1 do A[i]:=0M1: (r0,w1) means for i = 0 to n-1 do {read A[i]; A[i]:=1} M2: (r1,w0) means for i = n-1 to 0 do {read A[i]; A[i]:=0}

3.12 Combinations of memory cell faultsA memory may contain: A single faultMultiple faults (6 cases of CFs shown; ai is a-cell, vj is v-cell)) can be:Unlinked: Faults do not interact (Cases a, b, c, e)Linked: Faults do interact (Cases d, f)Linked faults have a common victim

3.13 Linked coupling faultsCase a: Two unlinked CFids; detected by the march test{(w0); (r0,w1);(w0,w1);(r1)} M0 M1 M2 M3 CFid sensitized by w1 operation of M1 detected by r0 of M1 CFid sensitized by w1 of M2, detected by r1 of M3Case b: Linked CFidsCannot be detected by test of Case a (for unlinked CFids) because of maskingLinked faults require special, more complex, testsa1v1a2v2a1a2v1=v2

Case a:Case b:March elements

3.14 Address decoder faults (AFs)Functional faults in the address decoders:A. With a certain address, no cell will be accessedB. A certain address accesses multiple cellsC. A certain cell is accesses with multiple addresses D. Certain cells are accessed with their own and other addressesDifficult fault: Read operations may produce a random resultAxAyCx=0Cy=1AxAyCx=1Cy=1Reading from address Ay

3.15 Mapping read/write logic faultsThe reduced functional model consists of three blocksthe address decoderthe memory cell array (MCA)the read/write logic

Read/write logic faults can be mapped onto MCA faultsSAFs, TFs and CFs will de detected by tests for the MCA

3.16 Mapping address decoder faultsMarch tests for MCAFs detect AFs if they satisfy Cond. AFCond. AF: The march test has to contain the following march elements1. (rx,,wx*) This means either (r0,,w1) or (r1,,w0) 2. (rx*,,wx) Note: means any # of r or w operations

ProofEasy for Faults A, B and CFor Fault D the result of a read operation can be:A deterministic function (Logical AND or OR) of read valuesA random result (when the read cells contain different values)

3.17 Mapping address decoder faults (cont.)Fault D: read result random if cells contain different valuesCond. AF-1: (rx,,wx*) detects Faults D1 & D2When Ax written with x*, cells Cy...Cz are also written with x*Fault detected when Cy is read: reads x* while expecting xCond. AF-2: (rx*,,wx) detects Faults D1 & D3When Ax written with x, cells Cv...Cw are also written with xFault detected when Cw is read: reads x while expecting x*.

Fault D2Fault D1Fault D3Original Fault D

4.1 Functional RAM chip testingPurpose1. Cover traditional tests (5)Zero-One (MSCAN)CheckerboardGALPAT and Walking 1/02. Cover tests for stuck-at, transition and coupling faults (6)MATS and MATS+March C-March A and March B3. Comparison of march tests (1)

4.2 Fault coverage of testsWhen a test detects faults of a particular fault type, it detects:all subtypes of that type; e.g., if it detects TFs is has to detect all and TFsall positions of each subtype (addr. a-cell < or > v-cell)A complete test detects all faults it is designed forIt may, additionally, and unintentionally, detect also other faultsBut not all subtypes and not all positions of each of these faults

Example: MATS+ : {(w0);(r0,w1);(r1,w0)}Detects all AFsDetects all SAFsDetects all TFsDoes not detect all TFs MATS+ does not detect TFsFault coverage of MATS+

AFs, SAFs TFs

4.3 Traditional testsTraditional tests are older testsUsually developed without explicitly using fault modelsUsually they also have a relatively long test timeSome have special properties in terms of:detecting dynamic faultslocating (rather than only detecting) faultsMany traditional tests exist:1. Zero-One (Usually referred to as Scan Test or MSCAN)2. Checkerboard3. GALPAT and Walking 1/04. Sliding Diagonal5. Butterfly6. Many, many others

4.4 Zero-One test (Scan test, (M)SCAN)Minimal test, consisting of writing & reading 0s and 1s Step 1: write 0 in all cellsStep 2: read all cellsStep 3: write 1 in all cellsStep 4: read all cellsMarch notation for Scan test: {(w0);(r0);(w1);(r1)}Test length: 4*n operations; which is O(n)Fault detection capability: AFs not detectedCondition AF not satisfied: 1. (rx,,wx*) 2. (rx*,,wx)If address decoder maps all addresses to a single cell, then it can only be guaranteed that one cell is fault freeSpecial property: Stresses read/write & precharge circuits when Fast X addressing is used and sequence of write/read 0101.... data in a column!Fast XaddressingRowsRow 000000stripe 111111 000000 111111Checker 010101board 101010 010101 101010Columns

4.5 Checkerboard Is SCAN test, using checkerboard data background pattern Step 1: w1 in all cells-W w0 in all cells-BStep 2: read all cells Step 3: w0 in all cells-W w1 in all cells-BStep 4: read all cells

Test length: 4*2N operations; which is O(n)Fault detection capability:Condition AF not satisfied : 1. (rx,,wx*); 2. (rx*,,wx)If address decoder maps all cells-W to one cell, and all cells-B to another cell, then only 2 cells guaranteed fault freeSpecial property: Maximizes leakage between physically adjacent cells. Used for DRAM retention test!!Checkerboarddata backgroundStep1 pattern

BWBWWBWBBWBWWBWB

0101101001011010

4.6 GALPAT and Walking 1/0GALPAT and Walking 1/0 are similar algorithmsThey walk a base-cell through the memory After each step of the base-cell, the contents of all other cells is verified, followed by verification of the base-cellDifference between GALPAT and Walking 1/0 is when, and how often, the base-cell is read

Base cellBase cell

4.7 GALPAT and Walking 1/0: PropertiesTests can locate faultsGALPAT detects write recovery faults (Cause: slow addr. decoders)Test length: O(n2): Not acceptable for practical purposes Most coupling faults in a memory are due to sharinga WL and the column decoder: cells in the same row BLs and row decoder: cells in the same column Subsets of GALPAT and Walking I/O used (BC= Base-Cell)GALROW and WalkROW: Read Action on cells in row of BC

GALCOL and WalkCOL: Read Action on cells in column of BCTest length (assuming n1/2 rows and n1/2 columns): O(n3/2)Note: Test time for 4Mb 150 ns memoryFor O(n2) test = O(20 days), and for O(n3/2 ) test = O(14 sec.)

5.1 March testsThe simplest, and most efficient tests for detecting AFs, SAFs, TFs and CFs are march tests

The following march tests are covered:MATS+Detects AFs and SAFsMarch C-Detects AFs, SAFs, TFs, and unlinked CFins, CFsts, CFidsMarch ADetects AFs, SAFs, TFs, CFins, CFsts, CFids, linked CFids (but not linked with TFs) March B Detects AFs, SAFs, TFs, CFins, CFsts, CFids, linked CFids

5.2 MATS+MATS+ algorithm: {(w0);(r0,w1);(r1,w0)} Fault coverageAFs detected because MATS+ satisfies Cond. AF (When reads, accessing multiple cells, return a random value) Cond. AF: 1. (rx,,wx*) and 2. (rx*,,wx)(1) satisfied by: (r0,w1) and (2) by: (r1,w0)SAFs are detected: from each cell the value 0 and 1 is read Test length: 5*nNote: If fault model is symmetric with respect to 0/1, /, and with respect to address a-cell < v-cell and address a-cell > v-cell,then each march tests has 3 equivalent tests0s 1s: {(w0);(r0,w1);(r1,w0)} {(w1);(r1,w0);(r0,w1)}s s: {(w0);(r0,w1);(r1,w0)} {(w0);(r0,w1);(r1,w0)} 0s1s,ss: {(w1);(r1,w0);(r0,w1)}{(w1);(r1,w0);(r0,w1)}

5.3 March C-March C (Marinescu,1982): an 11*n algorithm{(w0);(r0,w1);(r1,w0);(r0);(r0,w1);(r1,w0);(r0)}It can be shown that middle (r0) march element is redundantMarch C- (van de Goor,1991): a 10*n algorithm{(w0);(r0,w1);(r1,w0);(r0,w1);(r1,w0);(r0)} M0 M1 M2 M3 M4 M5

Fault coverage of March C-AFs: Cond. AF satisfied by M1 and M4, or by M2 and M3SAFs: Detected by M1 (SA1 faults) and M2 (SA0 faults)TFs: TFs sensitized by M1, detected by M2 (and M3+M4) TFs sensitized by M2, detected by M3 (and M4+M5)CFins detectedCFsts detectedCFids detected (see proof)

5.4 March C- detects CFidsMarch C-: {(w0);(r0,w1);(r1,w0); (r0,w1);(r1,w0);(r0)} M0 M1 M2 M3 M4 M5Proof for detecting CFs are all similar. Analyze all cases:Relative positions of a-cell and v-cell1. address of a-cell < v-cell; 2. address of a-cell > v-cellFault subtypea. CFid ; b. CFid ; c. CFid ; d. CFid

Consider Case 1a: a-cell < v-cell and CFid Fault sensitized by M3 and detected by M4If the CFid a1 (a-cell is a1) is linked to CFid a2, and address of a2 < a1 then linked fault will not be detectedReason: M3 will sensitize both faults, such that masking occursLinked fault

5.5 March A & March BMarch A algorithm (Suk,1981) {(w0);(r0,w1,w0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)} M0 M1 M2 M3 M4March A (Test length: 15*n) detectsAFs, SAFs, TFs, CFins, CFsts, CFidsLinked CFids, but not linked with TFs March A is complete: detects all intended faultsMarch A is irredundant: no operation can be removedMarch B algorithm (Test length: 17*n) {(w0);(r0,w1,r1,w0,r0,w1);(r1,w0,w1);(r1,w0,w1,w0);(r0,w1,w0)} M0 M1 M2 M3 M4Detects all faults of March A Detects CFids linked with TFs, because M1 detects all TFs

5.6 Test requirements for detecting SOpFsAn SOpF is caused by an open WL which makes the cell inaccessibleTo detect SOpFs, assuming a non-transparent sense amplifier, a march test has to verify that a 0 and a 1 has to be read from every cellThis will be the case when the march test contains the March Element ME of the form: (, rx, , rx*, ), for x = 0 and x = 1. This ME may be broken down into two MEs of the form: (,rx,) & (, rx*,), for for x = 0 and x = 1.Example: The ME (r0,w1,r1,w0,r0,w1) satisfies the above requirement

Note: Any test can be changed to detect SOpFs by making sure that the above requirement is satisfied by possibly adding a rx and/or a rx* operation to a MEExample: MATS+ {(w0);(r0,w1);(r1,w0)} becomes {(w0);(r0,w1,r1); (r1,w0,r0)}

5.7 Test requirements for detecting DRFsAny march test can be extended to detect DRFsEvery cell has to be brought into one stateA time period (Del) has to be waited for the fault to developNote: The time for Del is typically between 100 and 500 msThe cell contents has to be verified (should not be changed)Above three steps to be done for both states of the every cell

Example: MATS+ {(w0);(r0,w1);(r1,w0)} becomes {(w0);Del;(r0,w1);Del;(r1,w0)}

6.1 Pseudo-Random PR memory tests PurposeExplain concept of pseudo-random (PR) testing (1)Compute test length of PR tests for SAFs and k-CFs (5)Evaluation of PR tests (3)PR pattern generators and test response evaluators (2)

Sources of materialMazumder, P. and Patel, J.H. (1992). An Efficient Design of Embedded Memories and their Testability Analysis using Markov Chains. JETTA, Vol. 3, No. 3; pp. 235-250Krasniewski, A. and Krzysztof, G. (1993). Is There Any Future for Deterministic Self-Test of Embedded RAMs? In Proc. ETC93; pp. 159-168van de Goor, A.J. (1998). Testing Semiconductor Memories, Theory and Practice. ComTex Publishing, Gouda, The Netherlandsvan de Goor, A.J. and de Neef, J. (1999). Industrial Evaluation of DRAM Tests. In Proc. Design and Test in Europe (DATe99), March 8-13, Munich; pp. 623-630van de Goor, A.J. and Lin, Mike (1997). The Implementation of Pseudo-Random Tests on Commercial Memory Testers. In Proc. IEEE Int. Test Conf., Washington DC, 1997, pp. 226-235

6.2 Concepts of PR memory testingDeterministic testsControl & Reference data for the RAM under test have predetermined valuesThe Response data of the RAM under test is compared with the expected data, in order to make Pass/Fail decision

Pseudo-random testsControl data on some or all inputs established pseudo-randomlyReference data can be obtained from a Reference RAM or, as shown, from as compressor

6.3 Concepts of PR memory testingMemory tests usecontrol values for: Address lines (N)R/W line (1)write data values (B)

Deterministic test method Uses deterministic control and write data valuesIn a test the following can be Deterministic (D) or PR (R)The Address (A): DA or RAThe Write (W) operation: DW or RWThe Data (D) to be written: DD or RD MATS+ is a DADWDD (Det. Addr, Det. Write, Det. Data) testIn a PR test at least ONE component has to be PRThis can be: A (Addr.) &/or W (Write oper.) &/or D (Dat) PR tests are preferred above random tests: PR tests are repeatable

6.4 Pseudo-random tests for SAFsSome probabilities for computing the test length (TL)The TL is a function of the escape probability ep: probability that a line has the value 1pa: probability that an address line has the value 1pd: probability that a data line has the value 1pw: probability that the write line has the value 1pA: probability of selecting address A (with z 0s and N-z 1s)pA = (1- pa)z * pa(N-z)p1: probability of writing 1 to address A; p1 = pd * pw * pAp0: prob. of writing 0 to address A; p0 =(1- pd )* pw * pApr: probability of reading address A; pr = (1- pw )* pA

6.5 Test length of PR test for SAFsMarkov chain for detecting a SA0 fault (SA1 fault is similar)S0 : state in which a 0 is stored in the cellS1 : state in which a 1 should be in the cellSD0 : state in which SA0 fault is detected (absorbing state)pS0(t) : probability of being in state S0 at time tInitial conditions: pS0(0) =1-pI1, pS1(0) = pI1 , pSD0(0) =0

pS0(t) = (1- p1)*pS0(t-1) + p0* pS1(t-1) pS1(t) = p1*pS0(t-1) + (1- p0 -pr)* pS1(t-1) pSD0(t) = pr*pS1(t-1) + pSD0(t-1)

1-(p0+pr)1

6.6 Test length of PR test for SAFsWith deterministic testing fault detected with certaintyWith PR testing fault detected with an escape probability e SA0 fault is detected when: pSD0(t) 1-e; T0(e) is TL for SA0 faultsT(e): The test length for SAFs is: T(e) = max(T0(e),T1(e))

Test length coefficientTest length coefficient: Independent of n & proportional with ln(e)

e

Memory size

n=32

n=1k

n=32k

n=1024k

0.1

17

17

17

17

0.01

33

33

33

33

0.001

48

48

48

48

0.0001

64

64

64

64

0.00001

80

80

80

80

6.7 Test length of PR tests for k-CFsPR tests for k-CFids; the k cells may be located anywhere For k =2 the test will be for CFids; for k >2 the for PSFsTo sensitize the CFid the k-2 cells require enabling value GFor k = 5, there are k-2 = 3 enabling cellsAssume G = 110 = g1g2g3 then pG = pd2*(1-pd)

Several PR tests for k-CFs exist (2 shown below)DADWRD (Det. Addr., Det. Write, PR Data)Step 1: (w?); Initialize memory with PR valuesStep 2: repeat t times: (r?,w?); Read and write new PR valueStep 3: (r?); Perform a final readRARWRD (PR Addr, PR Write, PR Data)Step 1: (w1); Initialize memoryStep 2: repeat t times {Generate PR Addr., perform read with pr=1-pw or a write with pw}CFid

6.8 Test length of PR tests for k-CFs

Observations Number of operations roughly doubles if k increases by 1 The DADARD test is more time efficient The RARWRD test will detect more unanticipated faults (Faults of unexpected or unknown fault models)Note: k= Neigborhood SizeTest length coefficients Fault coverage of RARWRD tests

k

pG

Test

pa=pd=pw=0.5; e=0.001

DADWRD

RARWRD

2

1

90

228

3

pd

202

449

4

pd2

424

891

5

pd3

866

1775

6.9 Test lengths: Deterministic -- PR testsObservations Note: ANPSFs have k-2 cells in only one position For simple fault models deterministic tests more efficient - Detect all faults of some fault models with e = 0 For complex fault models PR tests do exist - PR tests detect all faults of all fault models, however with e > 0

Fault

Test length coefficient

Deterministic

Pseudo-random

e=0.01

e=0.001

e=0.000001

SAF

5*n (MATS+)

33*n

46*n

93*n

CFid

10*n (March C-)

145*n

219*n

445*n

ANPSF k=3

28*n

294*n

447*n

905*n

APSF k=3

n+32*n*log2n

294*n

447*n

905*n

ANPSF k=5

195*n

1200*n

1805*n

3625*n

APSF k=5

?

1200*n

1805*n

3625*n

6.10 Strengths/weaknesses of PR testsDeterministic tests based on a-priory fault modelsModels usually restricted to the memory cell array5% of real defects not explained (Krasniewski, ETC93)Tests detect 100% of targeted faults onlyPseudo-random testsNot targeted towards a particular fault modelPR tests detect faults of all fault models; however, with some e > 0 Long test time: Test length (TL) proportional to ln(e) and 2k-2For CFids: 445*n (e = 10-5) versus 10*n (for March C-)Less of a problem for SRAMs (e.g.,1 Mwrd, 1ns, 1000n test takes1s)Random pattern resistant faultswith a large data state (e.g., bit line imbalance)requiring a large address/operation state (e.g., Hammer tests)Cannot locate faults easily (For laser/dynamic repair)Well suited for BISTVery useful for verification purposesUsed for production SRAM testing (together with deterministic tests)Unknown fault models, short time to volume, high speed SRAM