2 2 mosaic schematics document ufcbga/ufcpga northwood · mosaic schematics document ufcbga/ufcpga...
TRANSCRIPT
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2001-09-19
Mosaic Schematics Document
uFCBGA/uFCPGA Northwood
REV: 0.1
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1 37Wednesday, September 19, 2001
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Size Document Number Rev
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
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Compal confidentialModel Name :ADY13(Mosaic)
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File Name : LA-1271
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IDSEL:AD17(PIRQA#,GNT#3,REQ#3)
IDSEL:AD20(PIRQA/B#,GNT#2,REQ#2)
AC-LINK
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2 37Wednesday, September 19, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
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D D
C C
B B
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Compal Electronics, Inc.
Mosaic Midas
FDD
PS/2
Serial port
Parallel port
RJ45
OZ6912/TPS2211
Function
Model
3Com Lanchipset(3C920)
Note1: "@" means all model depop
YES YES
YES
NO
YES
YES
YES
YES
YES
YES
+3VALW
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
State
Signal
ON
+5VALW
+12VALW
+1.8VALW
+3V
+5V
+2.5V
+1.25V
+3VS
+5VS
+1.8VS
+1.5VS
+1.2VP
+CPU_CORE
ON ON
ON ON ON
ON ON
ON OFF
OFF
OFF
OFF OFF OFF
Power Managment table
YES YES
YES
S/Wdisable
NO
Note2: Removed serial port,because add 2nd Fan
SST-Build
RG82845 FW82801CAM
B1(QC42)A3(QC45)
CHIPS Rev CHIPS Rev
ADY13 LA-1271 0.1
Note & Revision
3 37Wednesday, September 19, 2001
Title
Size Document Number Rev
Date: Sheet of
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
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HD#52
HD#43
HD#14
HA#27
HA#14
HA#11
HD#41HD#40HD#39HD#38
HD#9
HA#22
HA#20
HA#12
HD#26HD#25
HD#63
HD#19
HD#15
HD#10
HREQ#4
HA#23
HA#17
HD#33
HD#16
HA#30
HA#21
HA#9
HA#3
HD#51HD#50
HD#42
HD#32HD#31HD#30
HD#12HA#16
HA#26
HA#24
HA#18
HD#62
HD#8
HD#6
HD#11
HD#5
HD#3
HA#31
HA#29
HD#57HD#56HD#55HD#54HD#53
HD#49HD#48HD#47HD#46HD#45HD#44
HD#18
HD#29
HD#1HD#0
HREQ#3
HD#28HD#27
HREQ#2HREQ#1HREQ#0
HA#28
HA#15
HA#7HA#6
HA#4
HD#24HD#23HD#22HD#21HD#20
HD#17
HD#13
HD#2
HA#25
HA#10
HA#5
HD#61HD#60
HD#7
HD#4
HA#13
HA#8
HD#59HD#58
HD#37HD#36HD#35HD#34
HA#19
CLK_HCLK#CLK_HCLK
HD#[0..63]
HREQ#[0..4]
HA#[3..31]
+CPU_CORE
+CPU_CORE
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R98 10K_04021 2
R31 51.1_1%1 2
NorthWood
Mobile
U4A
NorthWood
K2K4L6K1L3M6L2M3M4N1M1N2N4N5T1R2P3P4R3T2U1P6U3T4V2R6
W1T5U4V3
W2Y1
AB1
J1K5J4J3H3G1
AC1V5
AA3AC3
G2D2H6
G4
E2E3F3
B21B22A23A25C21D22B24C23C24B25G22H21C26D23J21D25H22E24G23F23F24E25F26D26L21G26H24M21L22J24K23H25M23N22P21M24N23M26N26N25R21P24R25R24T26T25T22T23U26U24U23V25U21V22V24W26Y26W25Y23Y24Y21AA25AA22AA24
A10
A12
A14
A16
A18
A20
A8
AA
10A
A12
AA
14A
A16
AA
18A
A8
AB
11A
B13
AB
15A
B17
AB
19A
B7
AB
9A
C10
AC
12A
C14
AC
16A
C18
AC
8A
D11
AD
13A
D15
AD
17A
D19
AD
7A
D9
AE
10A
E12
AE
14A
E16
AE
18A
E20
AE
6A
E8
AF
11A
F13
AF
15A
F17
AF
19A
F2
AF
21A
F5
AF
7A
F9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E12
E14
E16
E18
E20
E8
F11
H1
H4
H23
H26
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA
1A
A11
AA
13A
A15
AA
17A
A19
AA
23A
A26
AA
4A
A7
AA
9A
B10
AB
12A
B14
AB
16A
B18
AB
20A
B21
AB
24A
B3
AB
6A
B8
AC
11A
C13
AC
15A
C17
AC
19A
C2
AC
22A
C25
AC
5A
C7
AC
9A
D1
AD
10A
D12
AD
14A
D16
AD
18A
D21
AD
23A
D4
AD
8
AF22AF23
F13
F15
F17
F19
F9
E10
A#3A#4A#5A#6A#7A#8A#9A#10A#11A#12A#13A#14A#15A#16A#17A#18A#19A#20A#21A#22A#23A#24A#25A#26A#27A#28A#29A#30A#31A#32A#33A#34A#35
REQ#0REQ#1REQ#2REQ#3REQ#4ADS#
AP#0AP#1BINIT#IERR#
BNR#BPRI#BR0#
LOCK#
DEFER#HITM#HIT#
D#0D#1D#2D#3D#4D#5D#6D#7D#8D#9
D#10D#11D#12D#13D#14D#15D#16D#17D#18D#19D#20D#21D#22D#23D#24D#25D#26D#27D#28D#29D#30D#31D#32D#33D#34D#35D#36D#37D#38D#39D#40D#41D#42D#43D#44D#45D#46D#47D#48D#49D#50D#51D#52D#53D#54D#55D#56D#57D#58D#59D#60D#61D#62D#63
VC
C_0
VC
C_1
VC
C_2
VC
C_3
VC
C_4
VC
C_5
VC
C_6
VC
C_7
VC
C_8
VC
C_9
VC
C_1
0V
CC
_11
VC
C_1
2V
CC
_13
VC
C_1
4V
CC
_15
VC
C_1
6V
CC
_17
VC
C_1
8V
CC
_19
VC
C_2
0V
CC
_21
VC
C_2
2V
CC
_23
VC
C_2
4V
CC
_25
VC
C_2
6V
CC
_27
VC
C_2
8V
CC
_29
VC
C_3
0V
CC
_31
VC
C_3
2V
CC
_33
VC
C_3
4V
CC
_35
VC
C_3
6V
CC
_37
VC
C_3
8V
CC
_39
VC
C_4
0V
CC
_41
VC
C_4
2V
CC
_43
VC
C_4
4V
CC
_45
VC
C_4
6V
CC
_47
VC
C_4
8V
CC
_49
VC
C_5
0V
CC
_51
VC
C_5
2V
CC
_53
VC
C_5
4V
CC
_55
VC
C_5
6V
CC
_57
VC
C_5
8V
CC
_59
VC
C_6
1V
CC
_62
VC
C_6
3V
CC
_64
VC
C_6
5V
CC
_66
VC
C_6
7V
CC
_68
VC
C_6
9V
CC
_70
VC
C_7
1V
CC
_72
VC
C_7
4V
CC
_75
VC
C_7
6V
CC
_77
VC
C_7
8V
CC
_79
VC
C_8
0
VS
S_0
VS
S_1
VS
S_2
VS
S_3
VS
S_4
VS
S_5
VS
S_6
VS
S_7
VS
S_8
VS
S_9
VS
S_1
0V
SS
_11
VS
S_1
2V
SS
_13
VS
S_1
4V
SS
_15
VS
S_1
6V
SS
_17
VS
S_1
8V
SS
_19
VS
S_2
0V
SS
_21
VS
S_2
2V
SS
_23
VS
S_2
4V
SS
_25
VS
S_2
6V
SS
_27
VS
S_2
8V
SS
_29
VS
S_3
0V
SS
_31
VS
S_3
2V
SS
_33
VS
S_3
4V
SS
_35
VS
S_3
6V
SS
_37
VS
S_3
8V
SS
_39
VS
S_4
0V
SS
_41
VS
S_4
2V
SS
_43
VS
S_4
4V
SS
_45
VS
S_4
6V
SS
_47
VS
S_4
8V
SS
_49
VS
S_5
0V
SS
_51
VS
S_5
2V
SS
_53
VS
S_5
4V
SS
_55
VS
S_5
6
BCLK0BCLK1
VC
C_8
1V
CC
_82
VC
C_8
3V
CC
_84
VC
C_8
5
VC
C_7
3
HA#[3..31]<8>
HREQ#[0..4]<8>
HD#[0..63] <8>
HADS#<8>
HBPRI#<8>
HLOCK#<8>HBNR#<8>
HIT#<8>HITM#<8>
HDEFER#<8>
HBR0#<8>
CLK_HCLK<14>CLK_HCLK#<14>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Layout note :
R_A
R_B
Address:1001_110X
W=15mil
Thermal SensorMAX6654MEE
If used ITP port must depop
1. Place R_A and R_B near CPU.2. Place decoupling cap 220PF near CPU.(Within500mils)
GTL Reference Voltage
Place resistor <100mils fromCPU pin
Trace width>=7mila
Murata LQG21F4R7N00
All of these pinconnected inside
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5 37Monday, September 10, 2001
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Date: Sheet of
H_THERMDAH_THERMDC
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DBI#[0..3]
H_DPSLP#
H_DSTBN#3
H_DSTBN#0
H_IGNNE#
H_DBI#0
H_DSTBN#1
H_SMI#
H_DBI#1
H_DSTBP#0
H_NMIH_INTR
H_DSTBP#2H_DSTBP#1
H_A20M#
H_RESET#
H_DBI#2
H_THERMDC
H_PWRGDH_STPCLK#
H_DSTBN#2
H_INIT#
H_DBI#3
H_DSTBP#3
H_PROCHOT#
H_SLP#
H_VSSA
H_THERMDA
ITP_TCKITP_TDI
ITP_TMSITP_TRST#
H_F_FERR#
H_THERMTRIP#
ITP_TDIITP_TMSITP_TRST#ITP_TCK
ITP_PRDY#
ITP_PREQ#ITP_PRDY#ITP_BPM1ITP_BPM0
H_VCCIOPLL
H_VCCA
H_VSSA
TESTTHI8_10
H_A20M#
H_SMI#
H_IGNNE#
H_STPCLK#
H_DPSLP#
H_NMI
H_INIT#
H_INTR
H_F_FERR#
H_RESET#
H_PWRGD
PM_CPUPERF#
TESTTHI0_1
TESTTHI2_7
H_PROCHOT#H_THERMTRIP#
ITP_PREQ#
ITP_BPM1ITP_BPM0
+5VALW
+5VALW
+5VALW
+1.2VP
+H_GTLREF1
+CPU_CORE
+1.2VP
+CPU_CORE
+1.2VP
+H_GTLREF1
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+5VALW+VL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R124
10K_0402
12
C2312200PF
12
C229
.1UF_0402
12
R127
1K_0402
12
R125
10K_0402
12
R126 1K_040212
U12
MAX6654MEE
12345678 9
10111213141516NC
VCCDXPDXNNCADD1GNDGND NC
ADD0ALERT
SMBDATANC
SMBCLKSTBY
NC
R116
51.1_1%
12
R86
51.1_1%
12
C226
.1UF_0402
R108 56_04021 2
R113 56_04021 2
R107 51.1_1%12
RP23 8P4R_1.5K1 82 73 64 5
R111 51.1_1%
12
L17 4.7UH_80mA1 2
L16 4.7UH_80mA1 2
+ C2233UF_D2_16V
12
+ C3633UF_D2_16V
12
R82
49.9_1%
12
R79
100_1%
12
C165
1UF
C175
220PF
R18 1K_04021 2
R19 1K_04021 2
R32 1K_04021 2
R102 200_040212
R100 200_040212
R104 200_040212
R117 200_040212
R83 200_040212
R103 200_040212
R95 200_040212
R110 200_040212
R84 200_0402
12
R97 56_040212
R85 51.1_1%12
R89 300_040212
R96 200_040212
Mobile
NorthWood
U4B
NorthWood
F1G5F4
AB2J6
C6B6B2B5
AB23Y4
AD25D1E5
W5AB25
H2H5
C4B3
C1D4
D5F7E6
P1L24
J26K25K26L25
AE
11A
E13
AE
15A
E17
AE
19A
E22
AE
24A
E26
AE
7A
E9
AF
1A
F10
AF
12A
F14
AF
16A
F18
AF
20A
F26
AF
6A
F8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
AE
5A
E4
AE
3A
E2
AE
1
AA21AA6F20F6A22A7
AD24AA2AC21AC20AC24AC23AA20AB22U6W4Y3A6
F8
G21
G24
G3
G6
J2 J22
J25
J5 K21
K24
K3
K6
L1 L23
L26
L4 M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W2
1W
24
W3
W6
Y2
Y22
Y25
Y5
AD6AD5
AC6AB5AC4
Y6AA5AB4
E22K22R22W22
F21J23P23W23
AC26AD26
L5R5
E21G25P26V21
AE25
AD20A5
AE23
AF
4
A2
C3V6AB26
AD22A4
AD2AD3
AE
21A
F24
AF25AF3
RS#0RS#1RS#2RSP#TRDY#
A20M#FERR#IGNNE#SMI#PWRGOODSTPCLK#DPSLP#LINT0LINT1INIT#RESET#
DRDY#DBSY#
THERMDCTHERMDA
TDITCK
TDOTMSTRST#
COMP1COMP0
DP#0DP#1DP#2DP#3
VS
S_5
7V
SS
_58
VS
S_5
9V
SS
_60
VS
S_6
1V
SS
_62
VS
S_6
3V
SS
_64
VS
S_6
5V
SS
_66
VS
S_6
7V
SS
_68
VS
S_6
9V
SS
_70
VS
S_7
1V
SS
_72
VS
S_7
3S
KT
OC
C#
VS
S_7
5V
SS
_76
VS
S_7
7V
SS
_78
VS
S_7
9V
SS
_80
VS
S_8
1V
SS
_82
VS
S_8
3V
SS
_84
VS
S_8
5V
SS
_86
VS
S_8
7V
SS
_88
VS
S_8
9V
SS
_90
VS
S_9
1V
SS
_92
VS
S_9
3V
SS
_94
VS
S_9
5V
SS
_96
VS
S_9
7V
SS
_98
VS
S_9
9V
SS
_100
VS
S_1
01V
SS
_102
VS
S_1
03V
SS
_104
VS
S_1
05V
SS
_106
VS
S_1
07V
SS
_108
VS
S_1
09V
SS
_110
VS
S_1
11V
SS
_112
VS
S_1
13V
SS
_114
VS
S_1
15V
SS
_116
VS
S_1
17V
SS
_118
VS
S_1
19V
SS
_120
VS
S_1
21V
SS
_122
VS
S_1
23V
SS
_124
VS
S_1
25V
SS
_126
VS
S_1
27V
SS
_128
VID
0V
ID1
VID
2V
ID3
VID
4
GTLREF0GTLREF1GTLREF2GTLREF3
NC1NC2
TESTHI0TESTHI1TESTHI2TESTHI3TESTHI4TESTHI5TESTHI6TESTHI7TESTHI8TESTHI9
TESTHI10GHI#
VS
S_1
29V
SS
_130
VS
S_1
31V
SS
_132
VS
S_1
33V
SS
_134
VS
S_1
35V
SS
_136
VS
S_1
37V
SS
_138
VS
S_1
39V
SS
_140
VS
S_1
41V
SS
_142
VS
S_1
43V
SS
_144
VS
S_1
45V
SS
_146
VS
S_1
47V
SS
_148
VS
S_1
49V
SS
_150
VS
S_1
51V
SS
_152
VS
S_1
53V
SS
_154
VS
S_1
55V
SS
_156
VS
S_1
57V
SS
_158
VS
S_1
59V
SS
_160
VS
S_1
61V
SS
_162
VS
S_1
63V
SS
_164
VS
S_1
65V
SS
_166
VS
S_1
67V
SS
_168
VS
S_1
69V
SS
_170
VS
S_1
71V
SS
_172
VS
S_1
73V
SS
_174
VS
S_1
75V
SS
_176
VS
S_1
77V
SS
_178
VS
S_1
79V
SS
_180
VS
S_1
81
BSEL0BSEL1
BPM#0BPM#1BPM#2BPM#3BPM#4BPM#5
DSTBN#0DSTBN#1DSTBN#2DSTBN#3
DSTBP#0DSTBP#1DSTBP#2DSTBP#3
ITP_CLK0ITP_CLK1
ADSTB#0ADSTB#1
DBI#0DBI#1DBI#2DBI#3
DBR#
VCCAVCCSENSEVCCIOPLL
VC
CV
ID
THERMTRIP#
PROCHOT#MCERR#
SLP#
VSSAVSSSENSE
NC3NC4
NC
5N
C6
NC7NC8
Q41
3904
23
1 R114
470_0402
1 2
Q39
3904
23
1
R382
470_0402
12
Q11
3904
23
1 R115
470_0402
1 2
Q14
3904
23
1
R118
470_0402
12R119
300_0402
12
R337
1K_0402
12
R105 51.1_1%12
R106 51.1_1%
12
G
D S
Q13@2N7002
2
1 3
TP3
1
TP2 1
SMB_EC_DA1 <7,15,28,29,33>
SMB_EC_CK1 <7,15,28,29,33>
THRM# <29>
H_RS#0<8>H_RS#1<8>H_RS#2<8>
H_TRDY#<8>
H_A20M#<16>
H_PWRGD<16>
H_F_FERR#<16>
H_RESET#<8>
H_SMI#<16>H_IGNNE#<16>
H_NMI<16>
H_STPCLK#<16>
H_INIT#<16>
H_INTR<16>H_DPSLP#<16>
H_DBSY#<8>H_DRDY#<8>
H_BSEL0<14>H_BSEL1<14>
CPU_VR_VID4 <6>
CPU_VR_VID1 <6>CPU_VR_VID2 <6>
CPU_VR_VID0 <6>
CPU_VR_VID3 <6>
H_DSTBN#[0..3] <8>
H_DSTBP#[0..3] <8>
H_ADSTB#0 <8>H_ADSTB#1 <8>
H_DBI#[0..3] <8>
H_SLP# <16>
PM_CPUPERF# <16>
PROCHOT#<29>
SHDN#<33,35>
CLK_ITPP<14>CLK_ITPP#<14>
ITP_DBR# <7>
PCIRST#<8,15,16,20,21,26,27,28>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EMI Clip PAD for CPU
Layout note :
Place .22uF caps underneath balls on solder side.
Use 2~3 vias per PAD.Place 10uF caps on the peripheral near balls.
Place close to CPU, Use 2~3 vias per PAD.
Please place these cap in the socket cavity area
CPU Voltage ID
PM_GMUXSEL = 0 : for low Voltage A-C1 : for high Voltage B-C
Please place these cap on the socket north side
Please place these cap on the socket south side
Used ESR 25m ohm cap total ESR=2.5m ohm
Layout note :
Place close to CPU power andground pin as possible(<1inch)
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6 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
CPU_VID3CPU_VID2CPU_VID1CPU_VID0
CPU_VID4
+CPU_CORE
+CPU_CORE+CPU_CORE
+3VS
+5VS
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PAD2
PAD-2.5X3
1
PAD6
PAD-2.5X3
1
C46.22UF_X7R
12
C47.22UF_X7R
12
C45.22UF_X7R
12
C48.22UF_X7R
12
C49.22UF_X7R
12
C31.22UF_X7R
12
C35.22UF_X7R
12
C33.22UF_X7R
12
C18110UF_6.3V_1206_X5R
12
C19810UF_6.3V_1206_X5R
12
C18310UF_6.3V_1206_X5R
12
+ C177220UF_D2_4V_25m
12
+ C223@220UF_D2_4V_25m
12
C32.22UF_X7R
12
C34.22UF_X7R
12
C18210UF_6.3V_1206_X5R
12
C19910UF_6.3V_1206_X5R
12
[email protected]_0402
12
U5
@SN74CBT3383
1
23
4 5
67
8 9
1011
1213
14 15
1617
18 19
2021
22 23
24BE#
C0A0
B0 D0
C1A1
B1 D1
C2A2
GNDBX
B2 D2
C3A3
B3 D3
C4A4
B4 D4
VCC
RP48P4R_10K
18
27
36
45
R4310K_0402
12
C18510UF_6.3V_1206_X5R
12
C20110UF_6.3V_1206_X5R
12
C20010UF_6.3V_1206_X5R
12
C18410UF_6.3V_1206_X5R
12
C20210UF_6.3V_1206_X5R
12
C2110UF_6.3V_1206_X5R
12
C2310UF_6.3V_1206_X5R
12
C3010UF_6.3V_1206_X5R
12
C3710UF_6.3V_1206_X5R
12
C1710UF_6.3V_1206_X5R
12
C5910UF_6.3V_1206_X5R
12
C6710UF_6.3V_1206_X5R
12
C7710UF_6.3V_1206_X5R
12
C21010UF_6.3V_1206_X5R
12
C21410UF_6.3V_1206_X5R
12
C19210UF_6.3V_1206_X5R
12
C18010UF_6.3V_1206_X5R
12
C20310UF_6.3V_1206_X5R
12
C17410UF_6.3V_1206_X5R
12
C19110UF_6.3V_1206_X5R
12
C17810UF_6.3V_1206_X5R
12
C18610UF_6.3V_1206_X5R
12
C17310UF_6.3V_1206_X5R
12
C17010UF_6.3V_1206_X5R
12
C20910UF_6.3V_1206_X5R
12
C20410UF_6.3V_1206_X5R
12
C21210UF_6.3V_1206_X5R
12
C17910UF_6.3V_1206_X5R
12
C19510UF_6.3V_1206_X5R
12
C19710UF_6.3V_1206_X5R
12
C18710UF_6.3V_1206_X5R
12
C21310UF_6.3V_1206_X5R
12
C20510UF_6.3V_1206_X5R
12
+ C172220UF_D2_4V_25m
12
+ C206220UF_D2_4V_25m
12
+ C56220UF_D2_4V_25m
12
+ C222@220UF_D2_4V_25m
12
+ C166220UF_D2_4V_25m
12
RP3
8P4R_0
1 82 73 64 5
R42 0_04021 2
PAD20
PAD-2.5X3
1
+ C164220UF_D2_4V_25m
12
+ C193220UF_D2_4V_25m
12
+ C190220UF_D2_4V_25m
12
AC_VID1<17>
AC_VID3<17>
AC_VID0<17>
PM_DPRSLPVR<16,32>
AC_VID2<17>
AC_VID4<17>
CPU_VR_VID3<5>
CPU_VR_VID1<5>
CPU_VR_VID4<5>
CPU_VR_VID2<5>
CPU_VID0 <32>CPU_VID1 <32>CPU_VID2 <32>CPU_VID3 <32>CPU_VID4 <32>
CPU_VR_VID0<5>
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
COMPAL Electronics,Inc
+5VS POWER
Fan1 Control circuit Fan2 Control circuit
Address:1001_000X
ADY13 LA-1271 0.1
LM75 Thermal sensor & Fan control
7 37Monday, September 10, 2001
Title
Size Document Number Rev
Date: Sheet of
+5VFAN +5VFAN2
+3VS
+12VALW
+3V
+5VALW
+12VALW
+3V
+5VALW
+5VALW
R208
240
R199 @0_0402
U23C
74HCT08
9
108
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D151SS355
21
D141N4148
21
Q192SA1036K
23
1
Q20FMMT619
23
1
R1693.48K_1%
12
C3482.2UF_16V_0805
12
D13
1N4148
21
R34610K_0402
12
JP16
53398-0310
123
C131
@1000PF_0402
R19010K_0402
12
R195 5.6K_04021 2
R194 100_04021 2
D81SS355
21
D31N4148
21
Q32SA1036K
23
1
Q9FMMT619
23
1
R83.48K_1%
12
C152.2UF_16V_0805
12
D9
1N4148
21
R7710K_0402
12
JP20
53398-0310
123
C160
@1000PF_0402
U9
LM75CIMMX-5
12
56
8
34
7SDASCL
A2A1
VCC
OS#GND
A0
C547.1UF_0402
12
R94 1K_04021 2
ITP_PWROK<30>PM_PWROK <16>
EN_DFAN<28>
FAN1_TACH <28>
EC_HPOWON <28>
EN_DFAN2<28>
FAN2_TACH <28>
SMB_EC_CK1<5,15,28,29,33>SMB_EC_DA1<5,15,28,29,33>
ITP_DBR#<5>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Place this cap near MCH
R_E
R_F
1. Place R_E and R_F near MCH2. Place decoupling cap 220PF near MCH pin.(Within500mils)
GTL Reference VoltageLayout note :
HUB Interface Reference
1. Place R_C and R_D in middle of Bus.2. Place capacitors near MCH.
Layout note :
R_C
R_D
Place closely pin P22
AGP_ST00=System memory is DDR1=System memory is SDR
Layout note :
Place this resistorclosely ball AE17
Place closelyball P26
Trace
width>=7mila
AGP_ST10=533Mhz1=400Mhz
Place this cap near AGP
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8 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
HREQ#[0..4]
HA#[3..31]HD#[0..63]
H_DBI#[0..3]
AGP_SBA[0..7]
AGP_AD[0..31] HUB_PD[0..10]
HA#27
HA#14
HA#11
HA#22
HA#20
HA#12
HREQ#4
HA#23
HA#17
HA#30
HA#21
HA#9
HA#3
HA#16
HA#26
HA#24
HA#18
HA#31
HA#29
HREQ#3HREQ#2HREQ#1HREQ#0
HA#28
HA#15
HA#7HA#6
HA#4
HA#25
HA#10
HA#5
HA#13
HA#8
HA#19
HD#52
HD#43
HD#14
HD#41HD#40HD#39HD#38
HD#9
HD#26HD#25
HD#63
HD#19
HD#15
HD#10
HD#33
HD#16
HD#51HD#50
HD#42
HD#32HD#31HD#30
HD#12
HD#62
HD#8
HD#6
HD#11
HD#5
HD#3
HD#57HD#56HD#55HD#54HD#53
HD#49HD#48HD#47HD#46HD#45HD#44
HD#18
HD#29
HD#1HD#0
HD#28HD#27
HD#24HD#23HD#22HD#21HD#20
HD#17
HD#13
HD#2
HD#61HD#60
HD#7
HD#4
HD#59HD#58
HD#37HD#36HD#35HD#34
CLK_GHT#CLK_GHT
H_DSTBN#3
H_DSTBN#0H_DSTBN#1
H_DSTBP#0
H_DSTBP#2H_DSTBP#1
H_DSTBN#2
H_DSTBP#3
H_DBI#0H_DBI#1H_DBI#2H_DBI#3
AGP_AD0AGP_AD1AGP_AD2AGP_AD3AGP_AD4AGP_AD5AGP_AD6AGP_AD7AGP_AD8AGP_AD9AGP_AD10AGP_AD11AGP_AD12AGP_AD13AGP_AD14AGP_AD15AGP_AD16AGP_AD17AGP_AD18AGP_AD19AGP_AD20AGP_AD21AGP_AD22AGP_AD23AGP_AD24AGP_AD25AGP_AD26AGP_AD27AGP_AD28AGP_AD29AGP_AD30AGP_AD31
AGP_FRAME#AGP_DEVSEL#AGP_IRDY#AGP_TRDY#AGP_STOP#AGP_PARAGP_REQ#AGP_GNT#
AGP_C/BE#0AGP_C/BE#1AGP_C/BE#2AGP_C/BE#3
AGP_PIPE#
AGP_ST0
AGP_ADSTB0AGP_ADSTB0#AGP_ADSTB1AGP_ADSTB1#AGP_SBSTBAGP_SBSTB#
AGP_ST1AGP_ST2
AGP_SBA0AGP_SBA1AGP_SBA2AGP_SBA3AGP_SBA4AGP_SBA5AGP_SBA6AGP_SBA7
CLK_AGP_MCH
AGP_RBF#AGP_WBF#
HUB_PD0HUB_PD1HUB_PD2HUB_PD3HUB_PD4HUB_PD5HUB_PD6HUB_PD7HUB_PD8HUB_PD9HUB_PD10
HLRCOMP
CLK_AGP_MCH
H_DSTBP#[0..3]H_DSTBN#[0..3]
H_SWNG0H_SWNG1
AGP_FRAME#AGP_TRDY#AGP_PARAGP_STOP#
AGP_GNT#AGP_REQ#AGP_IRDY#AGP_DEVSEL#
AGP_WBF#AGP_PIPE#AGP_RBF#
AGP_ST2
AGP_ADSTB0
AGP_ADSTB1
AGP_SBSTB
AGP_ADSTB0#
AGP_ADSTB1#
AGP_SBSTB#
AGP_ST0 AGP_ST1
+1.5VS
AGP_NBREF
+AGPREF
+VS_HUBREF
+CPU_CORE
+V_MCH_GTLREF
+1.8VS
+1.8VS
+VS_HUBREF
+CPU_CORE
+CPU_CORE
+1.5VS
+1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R121K_1%
12
R111K_1%
12
HO
ST
U10A
BROOKDALE(MCH-M)
AA2AB5AA5AB3AB4AC5AA3AA6AE3AB7AD7AC7AC6AC3AC8AE2AG5AG2AE8AF6AH2AF3AG3AE5AH7AH3AF4AG8AG7AG6AF8AH5AC11AC12AE9AC9AE10AD9AG9AC10AE12AF10AG11AG10AH11AG12AE13AF12AG13AH13AC14AF14AG14AE14AG15AG16AG17AH15AC17AF16AE15AH17AD17AE16
T4T5T3U3R3P7R2P4R6P5P3N2N7N3K4M4M3L3L5K3J2
M5J3L2H4N5G2M6L7
AE17
Y5Y3
W2W7W6
U6T7R7U5U2
AD4AE6AE11AC15AD3AE7AD11AC16
R5N6
U7Y4Y7
W5J27H26
V5V4
V3W3
V7
J8K8
AA7AD13
AD5AG4AH9
AD15
M7R8Y8AB11AB17
AC2AC13
HD#0HD#1HD#2HD#3HD#4HD#5HD#6HD#7HD#8HD#9
HD#10HD#11HD#12HD#13HD#14HD#15HD#16HD#17HD#18HD#19HD#20HD#21HD#22HD#23HD#24HD#25HD#26HD#27HD#28HD#29HD#30HD#31HD#32HD#33HD#34HD#35HD#36HD#37HD#38HD#39HD#40HD#41HD#42HD#43HD#44HD#45HD#46HD#47HD#48HD#49HD#50HD#51HD#52HD#53HD#54HD#55HD#56HD#57HD#58HD#59HD#60HD#61HD#62HD#63
HA#3HA#4HA#5HA#6HA#7HA#8HA#9HA#10HA#11HA#12HA#13HA#14HA#15HA#16HA#17HA#18HA#19HA#20HA#21HA#22HA#23HA#24HA#25HA#26HA#27HA#28HA#29HA#30HA#31
CPURST#
HIT#HITM#
RS#0RS#1RS#2
HREQ#0HREQ#1HREQ#2HREQ#3HREQ#4
HDSTBN#0HDSTBN#1HDSTBN#2HDSTBN#3HDSTBP#0HDSTBP#1HDSTBP#2HDSTBP#3
HADSTB#0HADSTB#1
HTRDY#DEFER#BPRI#HLOCK#RSTIN#TESTIN#DBSY#DRDY#
ADS#BNR#
BREQ#0
BCLKBCLK#
HSWNG0HSWNG1
DBI#0DBI#1DBI#2DBI#3
HVREF0HVREF1HVREF2HVREF3HVREF4
HRCOMP0HRCOMP1
AG
PH
UB
U10B
BROOKDALE(MCH-M)
R27R28T25R25T26T27U27U28V26V27T23U23T24U24U25V24Y27Y26
AA28AB25AB27AA27AB26
Y23AB23AA24AA25AB24AC25AC24AC22AD24
V25V23Y25
AA23
Y24W28W27W24W23W25
AG24AH25AF22
R24R23
AC27AC28AF27AF26
AG25AF24AG26
P25P24N27P23M26M25L28L27M27N28M24
N25N24
P27P26
AH28AH27AG28AG27AE28AE27AE24AE25
AE22AE23
P22
AD25
AA21
N22K27K5
L24M23
K7J26A3A7
A11A15
A19A23A27D5D9D13D17D21E1E4E26E29F8F12F16F20F24G26H9H11H13H15H17H19H21J1J4J6J22J29
G_AD0G_AD1G_AD2G_AD3G_AD4G_AD5G_AD6G_AD7G_AD8G_AD9G_AD10G_AD11G_AD12G_AD13G_AD14G_AD15G_AD16G_AD17G_AD18G_AD19G_AD20G_AD21G_AD22G_AD23G_AD24G_AD25G_AD26G_AD27G_AD28G_AD29G_AD30G_AD31
G_C/BE#0G_C/BE#1G_C/BE#2G_C/BE#3
G_FRAME#G_DEVSEL#G_IRDY#G_TRDY#G_STOP#G_PARG_REQ#G_GNT#PIPE#
AD_STB0AD_STB#0AD_STB1AD_STB#1SB_STBSB_STB#
ST0ST1ST2
HI_0HI_1HI_2HI_3HI_4HI_5HI_6HI_7HI_8HI_9
HI_10
HI_STBHI_STB#
HLRCOMPHI_REF
SBA0SBA1SBA2SBA3SBA4SBA5SBA6SBA7
RBF#WBF#
66IN
GRCOMP
AGPREF
VSS0VSS1VSS2VSS3VSS4VSS5VSS6VSS7VSS8VSS9VSS10
VSS11VSS12VSS13VSS14VSS15VSS16VSS17VSS18VSS19VSS20VSS21VSS22VSS23VSS24VSS25VSS26VSS27VSS28VSS29VSS30VSS31VSS32VSS33VSS34VSS35VSS36VSS37VSS38VSS39VSS40
R22
24.9_0603_1%
12
R25
24.9_0603_1%
12
R2336.5_1%12
R26
49.9_1%
12
R27
100_1%
12
C69
220PF
C42
1UF
R36 36.5_1%1 2
R90301_1%
12
R91301_1%
12
C196.01UF_0402
12
12
C208@470PF
12
R920_0402
12
C39.1UF_0402
12
C16.1UF_0402
12
C55@10PF_0402
R33@33_0402
12
R35301_1%
12
R37150_1%
12
C58.01UF_0402
12
R29301_1%
12
R24150_1%
12
C44.01UF_0402
12
RP20 @8P4R_8.2K1 82 73 64 5
RP21 @8P4R_8.2K1 82 73 64 5
RP22 @8P4R_8.2K1 82 73 64 5
R14 @6.2K_040212
R15 @6.2K_0402
12
R30 8.2K_040212
R20 8.2K_040212
R16 8.2K_040212
R17 @8.2K_040212
R21 @8.2K_040212
R34 @8.2K_040212
R13 2K_040212
R10 @0_040212
C57.01UF_0402
12
R9 @1K_040212
HA#[3..31]<4>
HREQ#[0..4]<4>
HD#[0..63] <4>
HADS#<4>
HBPRI#<4>HLOCK#<4>
HBNR#<4>
HIT#<4>HITM#<4>
HDEFER#<4>
H_RS#0<5>H_RS#1<5>H_RS#2<5>
H_TRDY#<5>
PCIRST#<5,15,16,20,21,26,27,28>
H_DBSY#<5>H_DRDY#<5>
H_ADSTB#0<5>H_ADSTB#1<5>
H_DBI#[0..3]<5>
HBR0#<4>
AGP_AD[0..31]<15>
AGP_C/BE#[0..3]<15>
AGP_ST[0..2]<15>
AGP_ADSTB0<15>
AGP_REQ#<15>
AGP_ADSTB0#<15>AGP_ADSTB1<15>
AGP_SBSTB#<15>AGP_SBSTB<15>AGP_ADSTB1#<15>
AGP_FRAME#<15>AGP_DEVSEL#<15>AGP_IRDY#<15>AGP_TRDY#<15>AGP_STOP#<15>AGP_PAR<15>
AGP_PIPE#<15>AGP_GNT#<15>
AGP_SBA[0..7] <15>
CLK_AGP_MCH <14>
AGP_RBF# <15>AGP_WBF# <15>
HUB_PD[0..10] <16>
HUB_PSTRB <16>HUB_PSTRB# <16>
CLK_GHT<14>CLK_GHT#<14>
H_DSTBP#[0..3] <5>H_DSTBN#[0..3] <5>
H_RESET#<5>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Layout note :
Trace width 5mil ; Spacing10milTrace A to ball U13/T13 orU17/T7 =1.5" Max
"Trace A"
"Trace A""Trace A"
"Trace A"
Layout notePlease closely pinJ21 and J9
Layout notePlace this capclosely pinJ28
Murata LQG21N4R7K10
Layout notePlace R_J closely BallH3<40mil,Ball H3 to G3 tracemustrouting 1"
R_J
EMI Clip PAD for MCH
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9 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
VSS_MCH_PLL0
DDR_SDQ[0..63]
DDR_CB[0..7]
DDR_SMA[0..12]
DDR_SDQ0DDR_SDQ1DDR_SDQ2DDR_SDQ3DDR_SDQ4DDR_SDQ5DDR_SDQ6DDR_SDQ7DDR_SDQ8DDR_SDQ9DDR_SDQ10DDR_SDQ11DDR_SDQ12DDR_SDQ13DDR_SDQ14DDR_SDQ15DDR_SDQ16DDR_SDQ17DDR_SDQ18DDR_SDQ19DDR_SDQ20DDR_SDQ21DDR_SDQ22DDR_SDQ23DDR_SDQ24DDR_SDQ25DDR_SDQ26DDR_SDQ27DDR_SDQ28DDR_SDQ29DDR_SDQ30DDR_SDQ31DDR_SDQ32DDR_SDQ33DDR_SDQ34DDR_SDQ35DDR_SDQ36DDR_SDQ37DDR_SDQ38DDR_SDQ39DDR_SDQ40DDR_SDQ41DDR_SDQ42DDR_SDQ43DDR_SDQ44DDR_SDQ45DDR_SDQ46DDR_SDQ47DDR_SDQ48DDR_SDQ49DDR_SDQ50DDR_SDQ51DDR_SDQ52DDR_SDQ53DDR_SDQ54DDR_SDQ55DDR_SDQ56DDR_SDQ57DDR_SDQ58DDR_SDQ59DDR_SDQ60DDR_SDQ61DDR_SDQ62DDR_SDQ63
DDR_CB0DDR_CB1DDR_CB2DDR_CB3DDR_CB4DDR_CB5DDR_CB6DDR_CB7
DDR_SCS#3
DDR_SCS#0DDR_SCS#1DDR_SCS#2
DDR_SDQS0DDR_SDQS1DDR_SDQS2DDR_SDQS3DDR_SDQS4DDR_SDQS5DDR_SDQS6DDR_SDQS7
DDR_SMA0DDR_SMA1DDR_SMA2DDR_SMA3DDR_SMA4DDR_SMA5DDR_SMA6
DDR_SMA8DDR_SMA9DDR_SMA10DDR_SMA11DDR_SMA12
DDR_SBS0DDR_SBS1
DDR_CKE0DDR_CKE1DDR_CKE2DDR_CKE3
DDR_SCAS#
DDR_SDQS8
DDR_SRAS#DDR_SWE#
DDR_SMA7
VSS_MCH_PLL1
VCC_MCH_PLL1VCC_MCH_PLL0
SM_RCOMP
RCVOUT#RCVIN#
+CPU_CORE
+2.5V
+1.5VS
+1.8VS
+1.25V
+1.5VS
SDREF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PO
WE
R/G
ND
U10D
BROOKDALE(MCH-M)
M8U8
AA9AB8
AB18AB20AC19AD18AD20AE19AE21AF18AF20AG19AG21AG23AJ19AJ21AJ23
A5A9
A13A17A21A25C1
C29D7
D11D15D19D23D25
F6F10F14F18F22G1G4
G29H8
H10H12H14H16H18H20H22H24K22K24K26L23K6J5J7
R22R29U22U26W22W29AA22AA26AB21AC29AD21AD23AE26AF23AG29AJ25
N14N16P13P15P17R14R16T15U14U16
L29N26L25M22N23
T17T13
U17U13
L1L4L6L8
L22L26N1N4N8
N13N15N17N29
P6P8
P14P16R1R4
R13R15R17R26
T6T8
T14T16T22U1U4
U15U29
V6V8
V22W1W4W8
W26Y6
Y22AA1
AA4AA8AA29AB6AB9AB10AB12AB13AB14AB15AB16AB19AB22AC1AC4AC18AC20AC21AC23AC26AD6AD8AD10AD12AD14AD16AD19AD22AE1AE4AE18AE20AE29AF5AF7AF9AF11AF13AF15AF17AF19AF21AF25AG1AG18AG20AG22AH19AH21AH23AJ3AJ5AJ7AJ9AJ11AJ13AJ15AJ17AJ27
VTT_0VTT_1VTT_2VTT_3VTT_4VTT_5VTT_6VTT_7VTT_8VTT_9VTT_10VTT_11VTT_12VTT_13VTT_14VTT_15VTT_16VTT_17VTT_18
VCCSM1VCCSM2VCCSM3VCCSM4VCCSM5VCCSM6VCCSM7VCCSM8VCCSM9VCCSM10VCCSM11VCCSM12VCCSM13VCCSM14VCCSM15VCCSM16VCCSM17VCCSM18VCCSM19VCCSM20VCCSM21VCCSM22VCCSM23VCCSM24VCCSM25VCCSM26VCCSM27VCCSM28VCCSM29VCCSM30VCCSM31VCCSM32VCCSM33VCCSM34VCCSM35VCCSM36VCCSM37VCCSM38
VCC1_5_0VCC1_5_1VCC1_5_2VCC1_5_3VCC1_5_4VCC1_5_5VCC1_5_6VCC1_5_7VCC1_5_8VCC1_5_9
VCC1_5_10VCC1_5_11VCC1_5_12VCC1_5_13VCC1_5_14VCC1_5_15
VCC1_5_16VCC1_5_17VCC1_5_18VCC1_5_19VCC1_5_20VCC1_5_21VCC1_5_22VCC1_5_23VCC1_5_24VCC1_5_25
VCC1_8_0VCC1_8_1VCC1_8_2VCC1_8_3VCC1_8_4
VCCGA1VCCHA1
VSSGA2VSSHA2
VSS41VSS42VSS43VSS44VSS45VSS46VSS47VSS48VSS49VSS50VSS51VSS52VSS53VSS54VSS55VSS56VSS57VSS58VSS59VSS60VSS61VSS62VSS63VSS64VSS65VSS66VSS67VSS68VSS69VSS70VSS71VSS72VSS73VSS74VSS75VSS76VSS77VSS78VSS79VSS80VSS81VSS82
VSS83VSS84VSS85VSS86VSS87VSS88VSS89VSS90VSS91VSS92VSS93VSS94VSS95VSS96VSS97VSS98VSS99
VSS100VSS101VSS102VSS103VSS104VSS105VSS106VSS107VSS108VSS109VSS110VSS111VSS112VSS113VSS114VSS115VSS116VSS117VSS118VSS119VSS120VSS121VSS122VSS123VSS124VSS125VSS126VSS127VSS128VSS129VSS130VSS131VSS132VSS133VSS134VSS135VSS136VSS137VSS138VSS139VSS140VSS141
ME
MO
RY
U10C
BROOKDALE(MCH-M)
G28F27C28E28H25G27F25B28E27C27B25C25B27D27D26E25D24E23C22E21C24B23D22B21C21D20C19D18C20E19C18E17E13C12B11C10B13C13C11D10E10C9D8E8
E11B9B7C7C6D6D4B3E6B5C4E5C3D3F4F3B2C2E2G5
C16D16B15C14B17C17C15D14
E14F15J24G25G6G7
G15G14E24G24H5F5
F26C26C23B19D12C8C5E3E15
E12F17
G18G19E18F19G21G20F21F13E20G22
G12G13
G23E22H23F23J23K23
K25J25G17G16H7H6
E9F7F9E7G9G10
J28
E16
G3H3
H27
F11G11G8
J21J9 AD26
AD27
SDQ0SDQ1SDQ2SDQ3SDQ4SDQ5SDQ6SDQ7SDQ8SDQ9SDQ10SDQ11SDQ12SDQ13SDQ14SDQ15SDQ16SDQ17SDQ18SDQ19SDQ20SDQ21SDQ22SDQ23SDQ24SDQ25SDQ26SDQ27SDQ28SDQ29SDQ30SDQ31SDQ32SDQ33SDQ34SDQ35SDQ36SDQ37SDQ38SDQ39SDQ40SDQ41SDQ42SDQ43SDQ44SDQ45SDQ46SDQ47SDQ48SDQ49SDQ50SDQ51SDQ52SDQ53SDQ54SDQ55SDQ56SDQ57SDQ58SDQ59SDQ60SDQ61SDQ62SDQ63
SDQ64/CB0SDQ65/CB1SDQ66/CB2SDQ67/CB3SDQ68/CB4SDQ69/CB5SDQ70/CB6SDQ71/CB7
SCK0SCK#0SCK1
SCK#1SCK2
SCK#2
SCK3SCK#3SCK4
SCK#4SCK5
SCK#5
SDQS0SDQS1SDQS2SDQS3SDQS4SDQS5SDQS6SDQS7SDQS8
SMA0/CS#11SMA1/CS#10
SMA3/CS#9SMA4/CS#5SMA5/CS#8SMA6/CS#7SMA7/CS#4SMA8/CS#3SMA9/CS#0
SMA10SMA11/CS#2SMA12/CS#1
SBS0SBS1
SCKE0SCKE1SCKE2SCKE3SCKE4SCKE5
SCK6SCK#6SCK7
SCK#7SCK8
SCK#8
SCS#0SCS#1SCS#2SCS#3SCS#4SCS#5
SMRCOMP
SMA2/CS#6
RCVENIN#RCVENOUT#
SSI_ST
SRAS#SWE#
SCAS#
SDREF0SDREF1 NC0
NC1
R39 27.4_1%12
R38 0_0402
12C78 .1UF_0402_X5R
C81 @47PF_0402
+ C9233UF_D2_16V
12
L18
4.7UH_30mA
12
L19
4.7UH_30mA
12
+ C9133UF_D2_16V
12
C72.1UF_0402_X5R
12
PAD10
PAD-2.5X3
1
PAD21
PAD-2.5X3
1
DDR_SDQ[0..63]<11>
DDR_CB[0..7]<11>
DDR_SDQS2 <11>DDR_SDQS3 <11>
DDR_SDQS1 <11>DDR_SDQS0 <11>
DDR_SDQS7 <11>DDR_SDQS6 <11>DDR_SDQS5 <11>DDR_SDQS4 <11>
DDR_SDQS8 <11>
DDR_SMA[0..12] <11,12>
DDR_SBS0 <11,12>DDR_SBS1 <11,12>
DDR_CKE2 <12>DDR_CKE3 <12>
DDR_CKE1 <11>DDR_CKE0 <11>
DDR_SCS#1 <11>
DDR_SCS#3 <12>
DDR_SCS#0 <11>
DDR_SCS#2 <12>
DDR_SCAS# <11,12>DDR_SWE# <11,12>DDR_SRAS# <11,12>
DDR_CLK0 <11>DDR_CLK0# <11>DDR_CLK1 <11>DDR_CLK1# <11>DDR_CLK2 <11>DDR_CLK2# <11>
DDR_CLK3 <12>DDR_CLK3# <12>DDR_CLK4 <12>DDR_CLK4# <12>DDR_CLK5 <12>DDR_CLK5# <12>
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Compal Electronics, Inc.
Layout note :
Distribute as close as possible to MCH Processor Quadrant.(between VTTFSB and VSS pin)
Layout note :
Distribute as close as possible to MCH Processor Quadrant.(between VCCAGP/VCCCOREand VSS pin)
Layout note :
Distribute as close as possible to MCH Processor Quadrant.(between VCCHL and VSS pin)
Hub-Link
AGP/CORE
Processor system busLayout note :
Distribute as close as possible to MCH Processor Quadrant.(between VCCSM and VSS pin)
DDR Memory interface
ADY13 LA-1271 0.1
MCH-M Decoupling
10 37Wednesday, September 19, 2001
Title
Size Document Number Rev
Date: Sheet of
+CPU_CORE
+CPU_CORE
+CPU_CORE
+1.5VS
+1.5VS
+1.8VS
+2.5V
+2.5V
+2.5V
+2.5V
C41.1UF_0402_X5R
12
C40.1UF_0402_X5R
12
C24.1UF_0402_X5R
12
C27.1UF_0402_X5R
12
C28.1UF_0402_X5R
12
C38.1UF_0402_X5R
12
C51.1UF_0402_X5R
12
C61.1UF_0402_X5R
12
C25.1UF_0402_X5R
12
C29.1UF_0402_X5R
12
C2010UF_6.3V_1206_X5R
12
C1910UF_6.3V_1206_X5R
12
C1810UF_6.3V_1206_X5R
12
C26.1UF_0402_X5R
12
C43.1UF_0402_X5R
12
C54.1UF_0402_X5R
12
C52.1UF_0402_X5R
12
C50.1UF_0402_X5R
12
C53.1UF_0402_X5R
12
C6510UF_6.3V_1206_X5R
12
C6010UF_6.3V_1206_X5R
12
C68.1UF_0402_X5R
12
C62.1UF_0402_X5R
12
C66.1UF_0402_X5R
12
C9022UF_10V_1206
12
C75.1UF_0402_X5R
12
C73.1UF_0402_X5R
12
C86.1UF_0402_X5R
12
C74.1UF_0402_X5R
12
C79.1UF_0402_X5R
12
C84.1UF_0402_X5R
12
C9422UF_10V_1206
12
C225.1UF_0402_X5R
12
C71.1UF_0402_X5R
12
C89.1UF_0402_X5R
12
C85.1UF_0402_X5R
12
C83.1UF_0402_X5R
12
C70.1UF_0402_X5R
12
C87.1UF_0402_X5R
12
C88.1UF_0402_X5R
12
C82.1UF_0402_X5R
12
+ C93150UF_D2_6.3V
12
C6410UF_6.3V_1206_X5R
12
+ C176100UF_D_16V
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
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A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
DIMM0
Layout note
Place these resistorclosely DIMM0,all trace length<750mil
Place these resistorclosely DIMM0,all trace length Max=1.3"
Layout note
Layout note
Place these resistorclosely DIMM0,all trace length<=750mil
Place these resistorclosely DIMM0,all tracelength<=750mil
Layout note
Bottomside
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11 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
DDR_SDQ0DDR_SDQ4
DDR_SDQ1DDR_SDQ5
DDR_SDQ6DDR_SDQS0
DDR_SDQ2DDR_SDQ3
DDR_SDQ8DDR_SDQ7
DDR_SDQ9DDR_SDQ12
DDR_SDQS1DDR_SDQ13
DDR_SDQ10DDR_SDQ14
DDR_SDQ15DDR_SDQ11
DDR_SDQ16DDR_SDQ20
DDR_SDQ21DDR_SDQ17
DDR_SDQ18DDR_SDQS2
DDR_SDQ19DDR_SDQ22
DDR_SDQ24DDR_SDQ23
DDR_SDQ25DDR_SDQ28
DDR_DQ0DDR_DQ4
DDR_DQ1DDR_DQ5
DDR_DQ6DDR_DQS0
DDR_DQ2DDR_DQ3
DDR_DQ8DDR_DQ7
DDR_DQ9DDR_DQ12
DDR_DQS1DDR_DQ13
DDR_DQ10DDR_DQ14
DDR_DQ15DDR_DQ11
DDR_DQ16DDR_DQ20
DDR_DQ21DDR_DQ17
DDR_DQ18DDR_DQS2
DDR_DQ19DDR_DQ22
DDR_DQ24DDR_DQ23
DDR_DQ25DDR_DQ28
DDR_SDQ30DDR_SDQ26
DDR_SDQ31DDR_SDQ27
DDR_CB5DDR_CB4
DDR_CB1DDR_CB0
DDR_CB2DDR_SDQS8
DDR_CB3DDR_CB6
DDR_CB7
DDR_SDQ36DDR_SDQ32
DDR_SDQ33DDR_SDQ37
DDR_SDQ38DDR_SDQS4
DDR_SDQ39DDR_SDQ34
DDR_SDQ44DDR_SDQ35
DDR_SDQ45DDR_SDQ40
DDR_SDQS5DDR_SDQ41
DDR_SDQ43DDR_SDQ42
DDR_DQ30DDR_DQ26
DDR_DQ31DDR_DQ27
DDR_F_CB5DDR_F_CB4
DDR_F_CB1DDR_F_CB0
DDR_F_CB2DDR_DQS8
DDR_F_CB3DDR_F_CB6
DDR_F_CB7
DDR_DQ36DDR_DQ32
DDR_DQ33DDR_DQ37
DDR_DQ38DDR_DQS4
DDR_DQ39DDR_DQ34
DDR_DQ44DDR_DQ35
DDR_DQ45DDR_DQ40
DDR_DQS5DDR_DQ41
DDR_DQ43DDR_DQ42
DDR_SDQS3DDR_DQ29DDR_DQS3
DDR_SDQ29DDR_SDQ47
DDR_DQ46DDR_DQ47
DDR_SDQ46
DDR_DQ4DDR_DQ5
DDR_DQ3
DDR_DQ7DDR_DQ12
DDR_DQ13
DDR_DQ14DDR_DQ11
DDR_DQ20DDR_DQ17
DDR_DQ22
DDR_DQ23DDR_DQ28
DDR_DQ29DDR_DQS3
DDR_DQ26DDR_DQ27
DDR_DQ36DDR_DQ33
DDR_DQ38
DDR_DQ39DDR_DQ44
DDR_DQ45
DDR_DQ43DDR_DQ47
DDR_DQ49DDR_DQ53
DDR_DQ54
DDR_DQ55DDR_DQ56
DDR_DQ60
DDR_DQ62DDR_DQ63
DDR_DQ0DDR_DQ1
DDR_DQ6
DDR_DQ2
DDR_DQ9
DDR_DQ8
DDR_DQ10DDR_DQ15
DDR_DQ16DDR_DQ21
DDR_DQ18
DDR_DQ19DDR_DQ24
DDR_DQ25
DDR_DQ30DDR_DQ31
DDR_DQ32DDR_DQ37
DDR_DQ34
DDR_DQ35DDR_DQ40
DDR_DQ41
DDR_DQ42DDR_DQ46
DDR_DQ48DDR_DQ52
DDR_DQ50
DDR_DQ51DDR_DQ57
DDR_DQ61
DDR_DQ58DDR_DQ59
DDR_SDQ49DDR_SDQ48
DDR_SDQ53DDR_SDQ52
DDR_SDQ54DDR_SDQS6
DDR_SDQ55DDR_SDQ50
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_F_CB7
DDR_F_CB6
DDR_F_CB4DDR_F_CB0 DDR_F_CB1
DDR_F_CB5
DDR_F_CB2
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_DQS8
DDR_CKE1 DDR_CKE0
DDR_CKE0
DDR_SCS#0 DDR_SCS#1
DDR_CKE1
DDR_SCS#0DDR_SCS#1
DDR_DQ[0..63]
DDR_SMA12DDR_SMA9
DDR_F_SMA12DDR_F_SMA9
DDR_SMA8DDR_SMA11
DDR_F_SMA8DDR_F_SMA11
DDR_SMA7DDR_SMA5
DDR_F_SMA7DDR_F_SMA5
DDR_SMA4DDR_SMA6
DDR_F_SMA4DDR_F_SMA6
DDR_SMA3DDR_SMA1
DDR_F_SMA3DDR_F_SMA1
DDR_SMA0DDR_SMA2
DDR_F_SMA0DDR_F_SMA2
DDR_SMA10 DDR_F_SMA10
DDR_SMA12DDR_SMA9
DDR_SMA7DDR_SMA5DDR_SMA3DDR_SMA1
DDR_SMA10
DDR_SMA11DDR_SMA8
DDR_SMA6DDR_SMA4DDR_SMA2DDR_SMA0
DDR_SBS0DDR_SWE#
DDR_SCAS#DDR_SRAS#
DDR_SBS1
DDR_F_SRAS#
DDR_F_SBS1
DDR_F_SWE#DDR_F_SBS0
DDR_F_SCAS#
DDR_SWE#DDR_SBS0
DDR_SBS1DDR_SRAS#DDR_SCAS#
DDR_F_CB3
DDR_DQ49
DDR_DQ54
DDR_DQ52DDR_DQ53
DDR_DQ50
DDR_DQS6
DDR_DQ48
DDR_DQ55
DDR_SDQ56DDR_SDQ51
DDR_DQ56DDR_DQ51
DDR_SDQ60DDR_SDQ57
DDR_DQ60DDR_DQ57
DDR_SDQS7DDR_SDQ61
DDR_DQS7DDR_DQ61
DDR_SDQ62DDR_SDQ58
DDR_DQ62DDR_DQ58
DDR_SDQ59 DDR_DQ59
DDR_CB[0..7]DDR_SDQ[0..63]
DDR_F_CB[0..7]DDR_DQS[0..8]
DDR_SDQS[0..8]
DDR_SDQ63 DDR_DQ63
+2.5V +2.5V
+1.25V
+3VS
SDREF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
JP22
DDR-SODIMM_200_Normal
13579
111315171921232527293133353739
414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143
246810121416182022242628303234363840
4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144
145147149151153155157159161163165167169171173175177179181183185187189191193195197199
146148150152154156158160162164166168170172174176178180182184186188190192194196198200
VREFVSSDQ0DQ1VDDDQS0DQ2VSSDQ3DQ8VDDDQ9DQS1VSSDQ10DQ11VDDCK0CK0#VSS
DQ16DQ17VDDDQS2DQ18VSSDQ19DQ24VDDDQ25DQS3VSSDQ26DQ27VDDCB0CB1VSSDQS8CB2VDDCB3DUVSSCK2CK2#VDDCKE1DU/A13A12A9VSSA7A5A3A1VDDA10/APBA0WE#S0#DUVSSDQ32DQ33VDDDQS4DQ34VSSDQ35DQ40VDD
VREFVSSDQ4DQ5VDDDM0DQ6VSSDQ7
DQ12VDD
DQ13DM1VSS
DQ14DQ15VDDVDDVSSVSS
DQ20DQ21VDDDM2
DQ22VSS
DQ23DQ28VDD
DQ29DM3VSS
DQ30DQ31VDDCB4CB5VSSDM8CB6VDDCB7
DU/RESET#VSSVSSVDDVDD
CKE0DU/BA2
A11A8
VSSA6A4A2A0
VDDBA1
RAS#CAS#
S1#DU
VSSDQ36DQ37VDDDM4
DQ38VSS
DQ39DQ44VDD
DQ41DQS5VSSDQ42DQ43VDDVDDVSSVSSDQ48DQ49VDDDQS6DQ50VSSDQ51DQ56VDDDQ57DQS7VSSDQ58DQ59VDDSDASCLVDD_SPDVDD_ID
DQ45DM5VSS
DQ46DQ47VDD
CK1#CK1VSS
DQ52DQ53VDDDM6
DQ54VSS
DQ55DQ60VDD
DQ61DM7VSS
DQ62DQ63VDDSA0SA1SA2DU
RP48 4P2R_221 42 3
RP24 4P2R_221 42 3
RP49 4P2R_221 42 3
RP25 4P2R_221 42 3
RP50 4P2R_221 42 3
RP26 4P2R_221 42 3
RP51 4P2R_221 42 3
RP27 4P2R_221 42 3
RP52 4P2R_221 42 3
RP29 4P2R_221 42 3
RP53 4P2R_221 42 3
RP30 4P2R_221 42 3
RP54 4P2R_221 42 3
RP31 4P2R_221 42 3
RP55 4P2R_221 42 3
RP56 4P2R_221 42 3
RP33 4P2R_221 42 3
RP57 4P2R_221 42 3
RP34 4P2R_221 42 3
RP58 4P2R_221 42 3
RP28 4P2R_221 42 3
RP68 4P2R_221 42 3
RP59 4P2R_221 42 3
RP39 4P2R_221 42 3
RP40 4P2R_221 42 3
RP60 4P2R_221 42 3
RP41 4P2R_221 42 3
RP61 4P2R_221 42 3
RP42 4P2R_221 42 3
RP62 4P2R_221 42 3
RP32 4P2R_221 42 3
RP43 4P2R_221 42 3
RP63 4P2R_221 42 3
RP44 4P2R_221 42 3
RP64 4P2R_221 42 3
RP45 4P2R_221 42 3
RP89 4P2R_561 42 3
RP94 4P2R_561 42 3
RP8 4P2R_101 42 3
RP35 4P2R_101 42 3
RP7 4P2R_101 42 3
RP36 4P2R_101 42 3
RP6 4P2R_101 42 3
RP37 4P2R_101 42 3
R44 10_04021 2
RP38 4P2R_101 42 3
R137 10_04021 2
RP5 4P2R_101 42 3
C260
.1UF_0402
12
RP65 4P2R_221 42 3
RP46 4P2R_221 42 3
RP66 4P2R_221 42 3
RP47 4P2R_221 42 3
RP67 4P2R_221 42 3
DDR_SDQS[0..8]<9>
DDR_DQS[0..8] <12>
DDR_CB[0..7]<9>
DDR_F_CB[0..7] <12>
DDR_CLK1<9>DDR_CLK1#<9>
DDR_CLK0<9>DDR_CLK0#<9>
DDR_CLK2 <9>DDR_CLK2# <9>
DDR_CKE0 <9>DDR_CKE1<9>
DDR_SCS#1 <9>DDR_SCS#0<9>
DDR_DQ[0..63] <12>
DDR_SMA[0..12] <9,12>
DDR_F_SMA[0..12]<12>
DDR_SBS0<9,12>DDR_SWE#<9,12>
DDR_SCAS#<9,12>DDR_SRAS#<9,12>
DDR_SBS1<9,12>
DDR_F_SBS0 <12>DDR_F_SWE# <12>
DDR_F_SCAS# <12>DDR_F_SRAS# <12>
DDR_F_SBS1 <12>
DIMM_SMDATA<12,14>DIMM_SMCLK<12,14>
DDR_SDQ[0..63]<9>
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��
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DIMM1
Place these resistorclosely DIMM1,all tracelength<=800mil
Layout note
Place these resistorclosely DIMM0,all trace lengthMax=1.3"
Layout note
EMI Clip PAD for Memory Door Top side
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12 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
DDR_DQ0DDR_DQ1
DDR_DQ6
DDR_DQ2DDR_DQ8
DDR_DQ9
DDR_DQ10DDR_DQ15
DDR_DQ16DDR_DQ21
DDR_DQ18
DDR_DQ19DDR_DQ24
DDR_DQ25DDR_DQS3
DDR_DQ30DDR_DQ31
DDR_DQ32DDR_DQ37
DDR_DQ34
DDR_DQ35DDR_DQ40
DDR_DQ41
DDR_DQ42DDR_DQ46
DDR_DQ48DDR_DQ52
DDR_DQ50
DDR_DQ51DDR_DQ57
DDR_DQ61
DDR_DQ58DDR_DQ59
DDR_DQ4DDR_DQ5
DDR_DQ3
DDR_DQ7
DDR_DQ13
DDR_DQ12
DDR_DQ14DDR_DQ11
DDR_DQ20DDR_DQ17
DDR_DQ22
DDR_DQ23DDR_DQ28
DDR_DQ29
DDR_DQ26DDR_DQ27
DDR_DQ36DDR_DQ33
DDR_DQ38
DDR_DQ39DDR_DQ44
DDR_DQ45
DDR_DQ43DDR_DQ47
DDR_DQ49DDR_DQ53
DDR_DQ54
DDR_DQ55DDR_DQ56
DDR_DQ60
DDR_DQ62DDR_DQ63
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_F_CB3
DDR_F_CB2
DDR_F_CB5DDR_F_CB1 DDR_F_CB0
DDR_F_CB4
DDR_F_CB6
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_DQS8
DDR_CKE3 DDR_CKE2
DDR_SCS#2 DDR_SCS#3
DDR_F_SMA12DDR_F_SMA9
DDR_F_SMA7DDR_F_SMA5DDR_F_SMA3DDR_F_SMA1
DDR_F_SMA10
DDR_F_SMA11DDR_F_SMA8
DDR_F_SMA6DDR_F_SMA4DDR_F_SMA2DDR_F_SMA0
DDR_F_SBS0DDR_F_SBS1DDR_F_SRAS#DDR_F_SCAS#
DDR_F_CB7
DDR_CKE3DDR_CKE2
DDR_SCS#2DDR_SCS#3
DDR_DQ[0..63]DDR_DQ0DDR_DQ4
DDR_DQ1DDR_DQ5
DDR_DQ6DDR_DQS0
DDR_DQ3DDR_DQ2
DDR_DQ8DDR_DQ7
DDR_DQ12DDR_DQ9
DDR_DQS1DDR_DQ13
DDR_DQ14DDR_DQ10
DDR_DQ15DDR_DQ11
DDR_DQ20DDR_DQ16
DDR_DQ17DDR_DQ21
DDR_DQS2DDR_DQ18
DDR_DQ25
DDR_DQ29
DDR_DQ19
DDR_DQ28
DDR_DQS3
DDR_DQ24DDR_DQ23
DDR_DQ22
DDR_DQ26DDR_DQ30
DDR_DQ31DDR_DQ27
DDR_F_CB5DDR_F_CB4
DDR_F_CB0DDR_F_CB1
DDR_DQS8DDR_F_CB2
DDR_F_CB3DDR_F_CB6
DDR_F_CB7
DDR_DQ32DDR_DQ36
DDR_DQ33DDR_DQ37
DDR_DQ38DDR_DQS4
DDR_DQ34
DDR_DQ44DDR_DQ35
DDR_DQ39
DDR_DQS5
DDR_DQ45
DDR_DQ46
DDR_DQ41
DDR_DQ42
DDR_DQ47
DDR_DQ43
DDR_DQ40
DDR_DQ48DDR_DQ49
DDR_DQ52DDR_DQ53
DDR_DQ54DDR_DQS6
DDR_DQ50DDR_DQ55
DDR_SBS0DDR_SWE#
DDR_SRAS#DDR_SCAS#
DDR_SBS1
DDR_SMA9DDR_SMA12
DDR_SMA11DDR_SMA8
DDR_SMA5
DDR_SMA4
DDR_SMA7
DDR_SMA6
DDR_SMA2
DDR_SMA3DDR_SMA1
DDR_SMA0
DDR_SMA10
DDR_DQ51DDR_DQ56
DDR_DQ57DDR_DQ60
DDR_DQ61DDR_DQS7
DDR_DQ58DDR_DQ62
DDR_F_SWE#
DDR_DQ59DDR_DQ63
DDR_SBS0DDR_SWE#
DDR_SCAS#DDR_SRAS#
DDR_SBS1
+2.5V +2.5V
+3VS
+1.25V
+1.25V +1.25V
+1.25V
+3VS
SDREF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PAD12
PAD-2.5X3
1
PAD18
PAD-2.5X3
1
PAD19
PAD-2.5X3
1
PAD11
PAD-2.5X3
1
PAD16
PAD-2.5X3
1
C123.1UF_0402
12
JP12
DDR-SODIMM_200_Reverse
13579
111315171921232527293133353739
414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143
246810121416182022242628303234363840
4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144
145147149151153155157159161163165167169171173175177179181183185187189191193195197199
146148150152154156158160162164166168170172174176178180182184186188190192194196198200
VREFVSSDQ0DQ1VDDDQS0DQ2VSSDQ3DQ8VDDDQ9DQS1VSSDQ10DQ11VDDCK0CK0#VSS
DQ16DQ17VDDDQS2DQ18VSSDQ19DQ24VDDDQ25DQS3VSSDQ26DQ27VDDCB0CB1VSSDQS8CB2VDDCB3DUVSSCK2CK2#VDDCKE1DU/A13A12A9VSSA7A5A3A1VDDA10/APBA0WE#S0#DUVSSDQ32DQ33VDDDQS4DQ34VSSDQ35DQ40VDD
VREFVSSDQ4DQ5VDDDM0DQ6VSSDQ7
DQ12VDD
DQ13DM1VSS
DQ14DQ15VDDVDDVSSVSS
DQ20DQ21VDDDM2
DQ22VSS
DQ23DQ28VDD
DQ29DM3VSS
DQ30DQ31VDDCB4CB5VSSDM8CB6VDDCB7
DU/RESET#VSSVSSVDDVDD
CKE0DU/BA2
A11A8
VSSA6A4A2A0
VDDBA1
RAS#CAS#
S1#DU
VSSDQ36DQ37VDDDM4
DQ38VSS
DQ39DQ44VDD
DQ41DQS5VSSDQ42DQ43VDDVDDVSSVSSDQ48DQ49VDDDQS6DQ50VSSDQ51DQ56VDDDQ57DQS7VSSDQ58DQ59VDDSDASCLVDD_SPDVDD_ID
DQ45DM5VSS
DQ46DQ47VDD
CK1#CK1VSS
DQ52DQ53VDDDM6
DQ54VSS
DQ55DQ60VDD
DQ61DM7VSS
DQ62DQ63VDDSA0SA1SA2DU
RP10 4P2R_561 42 3
RP9 4P2R_561 42 3
RP73 4P2R_561 42 3
RP74 4P2R_561 42 3
RP75 4P2R_561 42 3
RP76 4P2R_561 42 3
RP77 4P2R_561 42 3
RP78 4P2R_561 42 3
RP80 4P2R_561 42 3
RP79 4P2R_561 42 3
RP81 4P2R_561 42 3
RP19 4P2R_561 42 3
RP18 4P2R_561 42 3
RP82 4P2R_561 42 3
RP109 4P2R_561 42 3
RP16 4P2R_561 42 3
RP83 4P2R_561 42 3
RP17 4P2R_561 42 3
RP84 4P2R_56
1423
RP15 4P2R_56
1423
RP85 4P2R_56
1423
RP14 4P2R_56
1423
RP86 4P2R_56
1423
RP87 4P2R_56
1423
RP95 4P2R_56
1423
RP88 4P2R_56
1423
RP96 4P2R_56
1423
RP97 4P2R_56
1423
RP99 4P2R_56
1423
RP98 4P2R_56
1423
RP102 4P2R_56
1423
RP103 4P2R_56
1423
RP100 4P2R_56
1423
RP101 4P2R_56
1423
RP104 4P2R_56
1423
RP105 4P2R_56
1423
RP106 4P2R_56
1423
RP107 4P2R_56
1423
RP93 4P2R_56
1423
RP72 4P2R_56
1423
R142 56_04021 2
RP90 4P2R_56
1423
RP69 4P2R_56
1423
RP91 4P2R_56
1423
RP70 4P2R_56
1423
RP71 4P2R_56
1423
RP92 4P2R_56
1423
R160 56_04021 2
RP13 4P2R_56
1423
RP110 4P2R_56
1423
RP12 4P2R_56
1423
RP108 4P2R_56
1423
RP11 4P2R_56
1423
PAD7
PAD-2.5X3
1
PAD8
PAD-2.5X3
1
PAD14
PAD-2.5X3
1
DDR_CLK4<9>DDR_CLK4#<9>
DDR_CLK3<9>DDR_CLK3#<9>
DDR_CLK5 <9>DDR_CLK5# <9>
DDR_CKE2 <9>DDR_CKE3<9>
DDR_SCS#3 <9>DDR_SCS#2<9>
DDR_DQ[0..63] <11>
DDR_F_CB[0..7] <11>
DDR_F_SMA[0..12] <11>
DIMM_SMDATA<11,14>DIMM_SMCLK<11,14>
DDR_DQS[0..8] <11>
DDR_F_SBS0<11>DDR_F_SWE#<11>
DDR_F_SBS1 <11>DDR_F_SRAS# <11>DDR_F_SCAS# <11>
DDR_SMA[0..12] <9,11>
DDR_SBS0<9,11>DDR_SWE#<9,11>
DDR_SCAS#<9,11>DDR_SRAS#<9,11>
DDR_SBS1<9,11>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Layout note :
Distribute as close as possible to DDR-SODIMM.
Layout note :
Place one cap close to every 2 pull up resistors termination to+1.25V
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13 37Wednesday, September 19, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
+2.5V
+2.5V +2.5V
+1.25V
+1.25V
+1.25V
+1.25V
+1.25V
+1.25V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C98.1UF_0402_X5R
12
C118.1UF_0402_X5R
12
C97.1UF_0402_X5R
12
C111.1UF_0402_X5R
12
C102.1UF_0402_X5R
12
C99.1UF_0402_X5R
12
C119.1UF_0402_X5R
12
C121.1UF_0402_X5R
12
C120.1UF_0402_X5R
12
C113.1UF_0402_X5R
12
C76.1UF_0402_X5R
12
C100.1UF_0402_X5R
12
C101.1UF_0402_X5R
12
C105.1UF_0402_X5R
12
C104.1UF_0402_X5R
12
C103.1UF_0402_X5R
12
+ C122150UF_D2_6.3V
12
+ C117150UF_D2_6.3V
12
C299.1UF_0402_X5R
12
C300.1UF_0402_X5R
12
C303.1UF_0402_X5R
12
C302.1UF_0402_X5R
12
C301.1UF_0402_X5R
12
C326.1UF_0402_X5R
12
C298.1UF_0402_X5R
12
C325.1UF_0402_X5R
12
C304.1UF_0402_X5R
12
C324.1UF_0402_X5R
12
C332.1UF_0402_X5R
12
C297.1UF_0402_X5R
12
C294.1UF_0402_X5R
12
C250.1UF_0402_X5R
12
C305.1UF_0402_X5R
12
C331.1UF_0402_X5R
12
C330.1UF_0402_X5R
12
C295.1UF_0402_X5R
12
C306.1UF_0402_X5R
12
C293.1UF_0402_X5R
12
C253.1UF_0402_X5R
12
C251.1UF_0402_X5R
12
C114.1UF_0402_X5R
12
C311.1UF_0402_X5R
12
C309.1UF_0402_X5R
12
C308.1UF_0402_X5R
12
C307.1UF_0402_X5R
12
C252.1UF_0402_X5R
12
C312.1UF_0402_X5R
12
C310.1UF_0402_X5R
12
C315.1UF_0402_X5R
12
C319.1UF_0402_X5R
12
C329.1UF_0402_X5R
12
C316.1UF_0402_X5R
12
C318.1UF_0402_X5R
12
C314.1UF_0402_X5R
12
C313.1UF_0402_X5R
12
C320.1UF_0402_X5R
12
C328.1UF_0402_X5R
12
C317.1UF_0402_X5R
12
C291.1UF_0402_X5R
12
C296.1UF_0402_X5R
12
C115.1UF_0402_X5R
12
C292.1UF_0402_X5R
12
C284.1UF_0402_X5R
12
C322.1UF_0402_X5R
12
C286.1UF_0402_X5R
12
C323.1UF_0402_X5R
12
C321.1UF_0402_X5R
12
C285.1UF_0402_X5R
12
C287.1UF_0402_X5R
12
C290.1UF_0402_X5R
12
C289.1UF_0402_X5R
12
C288.1UF_0402_X5R
12
���
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A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
Place Crystal within 500 mils of CK_Titan
caps are internal to CK_TITAN
Width=40 mils
*BLM21A601SPT
Note:CPU_CLK[2:0] needs to be running in C3, C4.
Please closely pin42
or ICS 9508-05
SEL0SEL1 Function
0 0
0 1
1 0
1 1
66Mhz Host CLK
100Mhz Host CLK
200Mhz Host CLK
133Mhz Host CLK
Place resistor near R184,R185 ;Trace<=400mils
Place resistor near R182,R183 ;Trace<=400mils
Place resistor near R180,R181 ;Trace<=500mils
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14 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
CLK_ICH48M
CLKPCI_SIO
CLKPCI_F2
CLKICHHUBCLK66AGP
CLKPCI_LAN
CLK_ICH14M
H_BSEL2
CLKPCI_PCM
CLK_ITP
CLK_ITP#
CLKPCI_LPC
CLK_BCLK#
CLK_HT#
CLK_BCLK
DIMM_SMDATADIMM_SMCLK
CLK66MCH
CLK_HT
BSEL0H_BSEL0
+3VS
+3VS
+3VS
+3VS
+3V_CLK
+3VS_CLKVDD
+3VS
+3VS_VDD48M
+3VS
+5VS
+5VS
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R182 33.2_1%1 2
R183 33.2_1%1 2
R41 49.9_1%1 2
R40 49.9_1%1 2
R184 33.2_1%1 2
R185 33.2_1%1 2
R87 49.9_1%1 2
R88 49.9_1%1 2
R179 22_04021 2
R66 475_1%1 2
R215 33.2_1%1 2
R219 33.2_1%1 2
C381 @10PF_040212
C380 @10PF_040212
Y214.318MHZ
12
+C132
22UF_10V_1206
12
C388.1UF_0402
12
C364.1UF_0402
12
C385.1UF_0402
12
C139.1UF_0402
12
C137.1UF_0402
12
C382.1UF_0402
12
C386.1UF_0402
12
L21BLM21A601SPT1 2
C393.1UF_0402
12
R227 33.2_1%1 2R216 33.2_1%1 2
R186 33_04021 2
R177 33_04021 2
R63
1K_0402
12
R65@1K_0402
12
R591K_0402
12
R57 @10K_04021 2
R64 0_04021 2
R180 33.2_1%1 2
R181 33.2_1%1 2
R197 49.9_1%1 2
R196 49.9_1%1 2
U22
W320-04
1 8 14 19 32 37 46 50
26
4 9 15 20 31 36 41 47
273
2
405554
253453
28
43
2930
3335
42
45
44
49
48
52
51
24
232221
765
18171613121110
39
38
56
VD
D_R
EF
VD
D_P
CI
VD
D_P
CI
VD
D_3
V66
VD
D_3
V66
VD
D_4
8MH
ZV
DD
_C
PU
VD
D_C
PU
VDD_CORE
GN
D_R
EF
GN
D_P
CI
GN
D_P
CI
GN
D_3
V66
GN
D_3
V66
GN
D_4
8MH
ZG
ND
_IR
EF
GN
D_C
PU
GND_COREXTAL_OUT
XTAL_IN
SEL2SEL1SEL0
PWR_DWN#PCI_STOP#CPU_STOP#
VTT_PWRGD#
MULT0
SDATASCLK
3V66_0/DRCG3V66_1/VCH_CLK
IREF
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
66MHZ_IN/3V66_5
66MHZ_OUT2/3V66_466MHZ_OUT1/3V66_366MHZ_OUT0/3V66_2
PCICLK_F2PCICLK_F1PCICLK_F0
PCICLK6PCICLK5PCICLK4PCICLK3PCICLK2PCICLK1PCICLK0
48MHZ_USB
48MHZ_DOT
REFR223 33.2_1%1 2
L45BLM21A601SPT1 2
R61
1K_04021
2
R60
@1K_0402
12
L2210_0805
1 2
C138.1UF_0402
12
L48BLM21A601SPT1 2
C13310UF_10V_1206
12
C39610UF_10V_1206
12
R217 33.2_1%1 2
R58 10K_04021 2
R222 33.2_1%1 2R214 33.2_1%1 2
R394 @0_0402
1 2
G
D S
Q44 2N7002
2
1 3
R397 @1K_04021 2
G
D S
Q45 2N7002
2
1 3
CLK_GHT <8>
CLK_GHT# <8>
CLK_HCLK <4>
CLK_HCLK# <4>
CLK_ICH48<16>
SLP_S1#<16,28>PM_STPPCI#<16>
PM_STPCPU#<16,32>
CLK_ICHHUB <16>
CLK_ICHPCI <16>
CLK_ICH14<16>CLK_14M_SIO<26>
H_BSEL0<5>H_BSEL1<5>
CLK_ITPP <5>
CLK_ITPP# <5>
CK408_PWRGD#<30>
CLK_PCI_LAN <20>CLK_PCI_PCM <21>CLK_PCI_SIO <26>CLK_PCI_LPC <27>
CLK_AGP_MCH <8>CLK_AGP <15>
DIMM_SMCLK <11,12>
DIMM_SMDATA <11,12>SMB_DATA<16,18>
SMB_CLK<16,18>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CRT Connector
DDC_MONID0
AGP 140 Pin connector
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15 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
CRTB
CRTR
CRT_VSYNC
CRT_HSYNC
CRTG
3VDDCDA
M_SEN#
CRT_B
CRT_R
CRT_G
CRT_R
CRT_G
CRT_B
CRT_VSYNC3VDDCDA
CRT_HSYNC
AGP_SBA6AGP_SBA4AGP_SBA2AGP_SBA0 AGP_SBA5
AGP_SBA3
AGP_SBA7
AGP_SBA1AGP_ST0
3VDDCCL
AGP_AD30
AGP_AD26AGP_AD28 AGP_AD31
AGP_AD29
AGP_C/BE#3
AGP_AD24AGP_AD25AGP_AD27
AGP_C/BE#2AGP_AD23AGP_AD21
AGP_AD19AGP_AD17
AGP_AD22
AGP_AD18AGP_AD20
AGP_AD16
AGP_AD8
AGP_AD12AGP_AD10
AGP_AD14AGP_C/BE#1
AGP_AD13
AGP_AD9
AGP_AD15
AGP_AD11
AGP_C/BE#0AGP_AD7AGP_AD5AGP_AD3AGP_AD1
AGP_AD0AGP_AD2AGP_AD4AGP_AD6
AGP_RST#
M_SEN#
AGP_AD[0..31]
3VDDCCL
AGP_ST2
AGP_ST1VGA_DECT
VGA_DECT
+3VS
CRTVCC
+3VS
CRTVCC
+3VS
CRTVCC
CRTVCC
CRTVCC
+5VS
+12VALW
INVPWR_B+
+2.5V
+3V
+5V
+5VALW
+5VS
+1.5VS
+12VALW
+12VALW +5V +3VS +3V+2.5V+1.5VS +5VS +5VALW
B+
INVPWR_B+
+5V
+3VS
AGP_NBREF+AGPREF
+3V
AGP_NBREF
+AGPREF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R110K_0402
12
C153
3.3PF
12
C8
3.3PF
12
G
D S
Q12N7002
2
1 3
L1FBM-11-160808-121
1 2
R694.7K_0402
12
D7 @DAN217
1
2 3C151
.1UF_0402
12
C2
27PF
12
L11 FCM2012C-800(0805)1 2
L31
FCM2012C-800(0805)1 2
D1 @DAN217
1
2 3
JP2
CRT CONN.
61117
1228
1339
144
10155
R6
@75_1%
12
U774AHCT1G125GW
2 4
13
5
R5@75_1%
12
C5
100PF_0402
12
C6.1UF_0402
12
U1 74AHCT1G125GW
2 4
13
5
L23FBM-11-160808-121
1 2
C145.1UF_0402
12
C1
3.3PF
12
C3
100PF_0402
12
D2 @DAN217
1
2 3
L12
FCM2012C-800(0805)1 2
R70@75_1%
12
R34.7K_0402
12
R40_0402
12
R210K_0402
12
C4
100PF_0402
12
C146
100PF_0402
12
C150
27PF
12
G
D S
Q72N7002
2
1 3
C7
@3.3PF
12
C152
@3.3PF
12
C9
@3.3PF1
2
G
D
SQ2SI2302DS
2
13
G
D
SQ82N7002
2
13
R7
47K_0402
12
R73 100K_04021 2
JP8
FOXCONN_QTS0140A-1121_M140P_VGA
2468101214161820222426283032343638404244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140
13579
111315171921232527293133353739414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139
GND468
101214161820
GND242628303234363840
GND444648505254565860
GND6466687072747678
GND828486889092949698
GND102104106108110112114116118
GND122124126128130132134136138
GND
GND35791113151719GND232527293133353739GND434547495153555759GND6365676971737577GND818385878991939597GND101103105107109111113115117GND121123125127129131133135137GND
D4RB751V2 1
R99 0_04021 2
R101 @0_0402
1 2
C215.1UF_0402
12
C217.1UF_0402
12
C218.1UF_0402
12
C224.1UF_0402
12
C220.1UF_0402
12
C216.1UF_0402
12
C219.1UF_0402
12
C221.1UF_0402
12
R81
100K_0402
12
C168.1UF_0402
12
G
D
S
Q4
2N7002
2
13
R78
75K
12
Q10
FDS4435
3 65
78
2
4
1
R71
1K_0402
1 2
G
D
S
Q5
2N7002
2
13
R8010K_0402
12
CRT_ON#<29>
AGP_SBA[0..7]<8>
AGP_ST[0..2]<8>
AGP_C/BE#[0..3]<8>
SMB_EC_CK1 <5,7,28,29,33>SMB_EC_DA1 <5,7,28,29,33>INVT_PWM <28>DAC_BRIG <28>
AGP_SBSTB# <8>AGP_SBSTB <8>
AGP_ADSTB1<8>AGP_ADSTB1#<8>
AGP_ADSTB0<8>AGP_ADSTB0#<8>
AGP_PAR<8>AGP_IRDY#<8>
AGP_GNT#<8>AGP_TRDY#<8>
AGP_DEVSEL# <8>
PM_C3_STAT# <16>
AGP_PIPE#<8>AGP_BUSY#<16>
PIRQA# <16,18,21>AGP_FRAME# <8>AGP_STOP# <8>
ENABKL# <29>
AGP_RBF# <8>
AGP_AD[0..31]<8>
AGP_REQ#<8>
PCIRST# <5,8,16,20,21,26,27,28>CLK_AGP<14>
EC_AGPRST# <29>
BKOFF# <28>
AGP_WBF#<8>
SUS_STAT# <16,26>
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A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
(for use if CPU unable to support DPSLP#)
ICH3-M (1/2)InterfacePCI
InterfaceLAN
PCIInterface
HubLinkInterface
VSS
AC'97Interface
LPCInterface
Clocks EEPROMInterface
InterfaceCPU
Interface
SystemManagment
InterfaceInterrupt
GPIOunMUX
GeyservillePower Management
Place closely toICH3-M
Place closely toICH3-M
Close to ICH3-M.HUB Interface VSwing Voltage
1. Place R_G and R_H in middle of Bus.R_G
R_H
Layout note:Locate J1 and R265 on bottom side and witheasy access through memory door
HUB Reference Voltage
Place R_K and R_LClosely ICH3
R_K
R_L
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16 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
HUB_PD[0..10]
PIRQA#PIRQB#
PIRQD#PIRQC#
+R_VBAIS
AD27
AD16
AD13AD12
RTC_X1
GP
IO5
RT
C_X
2
ICH_WAKE_UP#
AD8
AD3AD2AD1
ICH
_L_O
UT
#
HUB_PD5
AD14
AD9
PIR
QB
#
PM_STPPCI#
HUB_PD0
AD26
AD20
AD17
AD11AD10
AD7AD6
CLK_ICH14
CLK_ICH14HUB_ICH_RCOMP
GP
IO3
HUB_PD10
HUB_PD4
H_FERR#
AD22
RT
C_V
BIA
S
HUB_PD9
HUB_PD3HUB_PD2
AD31AD30
AD21
RTC_VBIAS
RTC_X2
RT
C_X
1
CLK_ICH48
AD28
PBTN_OUT#
IDE
_P
AT
AD
ET
HUB_PD8
AD23
AD19
CLK_ICHPCI
GP
IO2
ICH
_S
CI#
HUB_PD6
HUB_PD1
CLK_ICHPCI
AD4
ICH_THRM#
PIR
QA
#
PIR
QC
#
GP
IO4
AD25AD24
EC
_SM
I#
AD29
PIR
QD
#
HUB_PD7
AD15
CLK_ICH48 RT
C_R
ST
#
AD18
AD5
AD0
IAC
_B
ITC
LK
AC
_R
ST
#S
DA
TA
_IN
0S
DA
TA
_IN
1S
DA
TA
O
IAC_BITCLK
SDATA_IN0
SDATA_IN1
IAC
_SY
NC
IAC_SDATAO
IAC_SYNC
EC_SMI#
ICH_SCI#
ICH_L_OUT#
ICH_THRM#
PBTN_OUT#
PM_PWROKBATTLOW#
BATTLOW#
IDE_PATADETS
DA
TA
O
PID
EP
WR
GPIO2
GPIO3
GPIO4
ICH_RI#
ICH_RI#
ICH_WAKE_UP#
AC_RST#
CLK_ICHHUB
CLK_ICHHUB
H_FERR#
GPIO5
+RTCVCC
+RTCVCC
+ICH_HUBREF
+VS_HUBVSWING
+CPU_CORE
+1.8VS
+VS_HUBVSWING
+3VS
+3VALW
+3VALW
+3VS
+3VS
+3VS
+3VALW
+3VS
+1.8VS
+ICH_HUBREF
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R295 36.5_1%1 2
R2251K_0402
12
C476.01UF_0402
12
C470.01UF_0402
12
R248@10K_0402
12
R243 10M1 2
C38312PF
12
R242 10M1 2
C415.047UF
1 2R234 1K_0402
1 2
X2
32.768KHZC38712PF
12
J1JOPEN
12
C408
1UF
12
R241 15K
1 2
C491
@15PF
12
R312
@10
12
R38310K_0402
12
C532 @33PF_04021 2
R362@22_0402
12
R363
33_0402
12
R257 33_040212
U35A
ICH3-M
J2K1J4K3H5K4H3L1L2G2L4H4M4J3
M5J1F5N2G4P2G1P1F2P3F3R1E2N4D1P4E1P5
K2K5N1R2
A4E3D2D5B4
D3F4A3R4E4
U22W23Y21AA23AB23AA21J22AB22V23Y22
AC5AB5AC4AB2AC3Y6
H1H2L5Y1W1M1M2G5N3B3B6D4C4F1M3T5
U23Y23W21
L22M21M23N20P21R22R20T23M19P19N19
T19
R19
N22
P23
K19
L20
L19
E9
D8
E8
D10
C8
A8
A9
B9
C10
A10
C9
D7
V4
Y5
AB
3V
5A
C2
AB
21A
B1
AA
6A
A1
AA
7W
20
AA
5A
A2
V21
U21
AA
4A
B4
U5
U20
Y20
V19
B7
D11
B11
C11
C7
A7
V1
U3
T3
U2
T2
U4
U1
V2
W2
Y4
Y2
W3
W4
Y3
AC
6A
C7
Y7
F20
J23
AB
7
H22
W1
9A
B14
A5
C5
B5
A6
A2
B2
C1
B1
J21
J20
J19
A1
A13
A16
A17
A20
A23
B8
B10
B13
B14
B15
B18
B19
B20
B22
C3
C6
F19
C14
C15
C16
C17
C18
C19
C20
C21
C22
D9
D13
D16
D17
D20
D21
D22
E5
PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28PCI_AD29PCI_AD30PCI_AD31
PCI_C/BE#0PCI_C/BE#1PCI_C/BE#2PCI_C/BE#3
PCI_GNT#0PCI_GNT#1PCI_GNT#2PCI_GNT#3PCI_GNT#4
PCI_REQ#0PCI_REQ#1PCI_REQ#2PCI_REQ#3PCI_REQ#4
CPU_RCIN#CPU_PWRGOOD
CPU_NMICPU_INTRCPU_INIT#
CPU_IGNNE#CPU_FERR#
CPU_DPSLP#CPU_A20M#
CPU_A20GATE
SMB_ALERT#/GPIO11SMB_DATA
SMB_CLKSMLINK1SMLINK0
SM_INTRUDER#
PCI_TRDY#STOP#
PCI_SERR#PCI_RST#PCI_PME#
PCI_LOCK#PCI_PERR#
PCI_PARPCI_IRDY#
PCI_GPIO17/GNTB#/GNT5#PCI_GPIO16/GNTA#
PCI_GPIO1/REQB#/REQ5#PCI_GPIO0/REQA#
PCI_FRAME#PCI_DEVSEL#
PCI_CLK
STPCLK#CPU_SMI#CPU_SLP#
HUB_PD0HUB_PD1HUB_PD2HUB_PD3HUB_PD4HUB_PD5HUB_PD6HUB_PD7HUB_PD8HUB_PD9
HUB_PD10
HU
B_C
LKH
UB
_PA
RH
UB
_P
ST
RB
HU
B_P
ST
RB
#H
UB
_RC
OM
PH
UB
_VR
EF
HU
B_V
SW
ING
EE
P_C
SE
EP
_D
INE
EP
_D
OU
TE
EP
_SH
CLK
LAN
_RX
D0
LAN
_RX
D1
LAN
_RX
D2
LAN
_TX
D0
LAN
_TX
D1
LAN
_TX
D2
LA
N_JC
LK
LAN
_RS
TS
YN
C
PM
_AG
PB
US
Y#/
GP
IO6
PM
_A
UX
PW
RO
KP
M_B
AT
LO
W#
PM
_C
3_S
TA
T#/G
PIO
21
PM
_CLK
RU
N#/
GP
IO24
PM
_DP
RS
LPV
RP
M_P
WR
BT
N#
PM
_P
WR
OK
PM
_RI#
PM
_RS
MR
ST
#P
M_S
LP_S
1#/G
PIO
19P
M_S
LP_S
3#P
M_S
LP_S
5#P
M_S
TP
CP
U#/G
PIO
20
PM
_S
TP
PC
I#/G
PIO
18
PM
_SU
S_C
LKP
M_S
US
_S
TA
T#
PM
_TH
RM
#
PM
_GM
UX
SE
L/G
PIO
23P
M_C
PU
PR
EF
#/G
PIO
22P
M_V
GA
TE
/VR
MP
WR
GD
AC
_B
ITC
LK
AC
_R
ST
#A
C_S
DA
TA
IN0
AC
_S
DA
TA
IN1
AC
_S
DA
TA
OU
TA
C_S
YN
C
LPC
_AD
0LP
C_A
D1
LPC
_AD
2LP
C_A
D3
LPC
_DR
Q#0
LPC
_DR
Q#1
LPC
_FR
AM
E#
GP
IO_7
GP
IO_8
GP
IO_1
2G
PIO
_13
GP
IO_2
5G
PIO
_27
GP
IO_2
8
CLK
_RT
CX
2C
LK_R
TC
X1
CLK
_R
TE
ST
#C
LK_4
8C
LK_1
4
CLK
_VB
IAS
INT
_S
ER
IRQ
INT
_IR
Q15
INT
_IR
Q14
INT
_P
IRQ
H#/G
PIO
5IN
T_P
IRQ
G#/G
PIO
4IN
T_P
IRQ
F#/G
PIO
3IN
T_P
IRQ
E#/G
PIO
2IN
T_P
IRQ
D#
INT
_P
IRQ
C#
INT
_P
IRQ
B#
INT
_P
IRQ
A#
INT
_A
PIC
D1
INT
_A
PIC
D0
INT
_A
PIC
CLK
VS
S0
VS
S1
VS
S2
VS
S3
VS
S4
VS
S5
VS
S6
VS
S7
VS
S8
VS
S9
VS
S10
VS
S11
VS
S12
VS
S13
VS
S14
VS
S15
VS
S16
VS
S17
VS
S18
VS
S19
VS
S20
VS
S21
VS
S22
VS
S23
VS
S24
VS
S25
VS
S26
VS
S27
VS
S28
VS
S29
VS
S30
VS
S31
VS
S32
VS
S33
VS
S34
R297301_1%
12
R281301_1%
12
C468.1UF_0402
12
R249 0_04021 2
D21
RB751V
21R263 10K_0402
1 2
D20
RB751V
21R259 10K_0402
1 2
D22
RB751V
21R267 10K_0402
1 2
D18
RB751V
21
R237
0_0402
1 2
D16 1SS355
21R221 10K_0402
1 2
R246 10K_04021 2
C543
@27PF
12
C544
@27PF
12
R364
22_0402
12
R372 @10K_04021 2
R387 10K_04021 2
R385 @10K_04021 2
R391 8.2K_04021 2
R392 8.2K_04021 2
R389 8.2K_04021 2
D19
RB751V
21
D29
RB751V
21
R348 10K_04021 2
R384
@1K_0402
12
R388 33_0402
1 2
R229 @22M1 2
12
C4505PF_0402
R26533_0402
12
R338
10_0402
12
C511
5PF_0402
12
R270
10_0402
12
C454
15PF
12
Q31
3904
23
1
Q32
3904
23
1
R318300_0402
12
R333470_0402
12
R307
470_0402
1 2
R298301_1%
12
R280301_1%
12
R390 8.2K_04021 2
R301 10K_04021 2
R28 10K_0402
1 2
CLK_ICH14<14>
PCIRST# <5,8,15,20,21,26,27,28>
LAD1 <26>
CLK_ICHPCI <14>
HUB_PSTRB <8>
GNT#1<18>
REQ#4<18>
PM_DPRSLPVR<6,32>
GNT#2<18,21>
LAD2 <26>
FRAME# <18,20,21,27>
C/BE#0<20,21,27>
LAD0 <26>
REQ#0<18>
C/BE#3<20,21,27>
HUB_PD[0..10] <8>
CLK_ICH48<14>
TRDY# <18,20,21,27>
LAD3 <26>
REQ#3<18,20>
HUB_PSTRB# <8>
C/BE#1<20,21,27>
REQ#1<18>
AD[0..31]<20,21,27>
PM_GMUXSEL<32>
C/BE#2<20,21,27>
CLK_ICHHUB <14>
IRDY# <18,20,21>
STOP# <18,20,21>
PCI_REQB# <18>PCI_REQA# <18>
PERR# <18,20,21>
REQ#2<18,21>
PAR <20,21>
DEVSEL# <18,20,21>
SIRQ <18,21,26>
LDRQ#0 <26>
KBRST# <28>
PM_CPUPERF#<5>
SM_INTRUDER# <18>
SMB_CLK <14,18>SMB_DATA <14,18>
PM_CLKRUN#<18,20,21,26> IRQ14 <18,19>IRQ15 <18,19>
SLP_S3#<28>SLP_S1#<14,28>
SLP_S5#<28>PM_STPCPU#<14,32>PM_STPPCI#<14>
SUS_STAT#<15,26>
H_DPSLP#<5>
SMB_ALERT# <18>
GATEA20 <28>
H_SMI# <5>
H_INIT# <5>
SMLINK1 <18>
H_NMI <5>
SMLINK0 <18>
H_STPCLK# <5>
H_INTR <5>
H_PWRGD <5>
H_IGNNE# <5>
ICH_VGATE<30>
PIRQA#<15,18,21>PIRQB#<18,20>PIRQC#<18>PIRQD#<18>
GNT#3<18,20>
AGP_BUSY#<15>
PM_C3_STAT#<15>
GNT#0<18>
IAC_BITCLK<23,25>
AC97_RST#<23,25>
SDATA_IN0<23>
RSMRST#<30>
RTCCLK
SDATA_IN1<25> SERR# <18,20,21>
PLOCK# <18,21>
GNT#4<18>
IAC_SYNC<23,25>
IAC_SDATAO<23,25>
PM_PWROK<7>
H_A20M# <5>
EC_SMI#<26,28>
SCI#<28>
LID_OUT#<29>
EC_THRM#<28>
PWRBTN_OUT#<29>
VLBA#<29>
SWI#<29>
EC_WAKEUP#<29>
LFRAME# <26>PIDEPWR <19>
ICH_RI#<18>
H_SLP# <5>
H_F_FERR#<5>
���
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��
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A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
ICH3-M (2/2) InterfaceIDE
InterfaceUSB
Misc
Power
Power
VSS
Layout note The Cap close toICH3-M(< 1 inch)
Disable Timeout feature
0=I2C CTRL CPUVID select1=Bus switch CPUVID select
M/B ID
MB_ID0 MB_ID1
SST
PT
ST
QT
0 0
01
10
1 1
Note:R376=22.6_1% for B0(QB63 part)R376=18.2_1% for B0(QB62 & SL5LF part)
Closely Pin AB6
*
����������� 0.1
*%����*�+���
17 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
SDD10
SDD1
PDD0
PDD9
SDD11
PDD6
PDD2
SDD8
SDD0
PDD3
PDD13PDD12
SDD12
OVCUR#1
PDD7
SDD13
PDD8
PDD1
SDD6
PDD11
SDD4
VCC5REF
SDD3SDD2
PDD5
USBP0-
AV_VID4
USBP0+
PDD4
SDD7
PDD10
SDD9
PDD15PDD14
SDD5
USBP2+
USBP2-
OVCUR#2OVCUR#3OVCUR#4OVCUR#5
ICH_SPKR
VC
C1.
8SU
S
VC
C1.
8SU
S
ICH_ACIN
ICH_ACIN
VC
CP
AU
USBP0-USBP0+
USBP2+
VC
CR
EF
SU
S
ICH_SPKR
USBP2-
OVCUR#5OVCUR#4OVCUR#3OVCUR#1
OVCUR#0
SDD15SDD14
ICH_IDE_SRST#
AV_VID4
MB_ID0MB_ID1
MB_ID0
MB_ID1
+5VS +3VS +3VALW
+3VALW
+CPU_CORE
+1.8VALW
+VCC_RTC
+V1.8_ICHLAN+1.8VALW
+3VS +1.8VS
+3VS
+3VALW
+1.8VS
+3VS
+3V
VCCPSUS
VCC1.8SUS
+5VS
+3VS
+3VS
+RTCVCC+VCC_RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
D171SS355
21
C5091UF
12
C418.1UF_0402
12
R2001K_0402
12
R34718.2_1%
12
L53
BLM21A601SPT
1 2
D32 RB751V21
R341
100K_0402
12
R371
0_0402
12
R361
0_08051 2
R376
0_0805
12
R374
0_0805
12
R369
0_08051 2
C534 5PF_04021 2
C535 5PF_04021 2
C539.1UF_0402
12
R308
@1K_0402
1 2
RP122
8P4R_10K
1 82 73 64 5
U35B
ICH3-M
D19A19E17B17D15A15D18A18E16B16D14A14
E12D12C12B12A12A11
H20G22F21G19E22E21H21G23F23G21D23E23
B21
AC15AB15AC21AC22
AA14AC14AA15AC20AA19AB20
W12AB11AA10AC10W11Y9AB9AA9AC9Y10W9Y11AB10AC11AA11AC12
Y17W17AC17AB16W16Y14AA13W15W13Y16Y15AC16AB17AA17Y18AC18
Y13Y19AB12AB18AC13AC19Y12AA18AB13AB19
H23
E13
F14
K12
P10
V6
V7
F15
F16
F7
F8
K10
AB
6
E6
W8
C13
W5
F9
F10
P14
U18
V22
C23
B23
E7
T21
D6
T1
C2
A21
A22
F6
G6
H6
J6 M10
R6
T6
U6
G18
H18
P12
V15
V16
V17
V18
J18
M14
R18
T18
U19
F17F18K14
E10V8V9
E11
K6
K18
P6
P18
V10
V14
E14
E15
E18
E19
E20
F22
G3
G20
H19
AA
22J5 K
11K
13K
20K
21K
22K
23L3 L1
0L1
1L1
2L1
3L1
4L2
1L2
3M
11M
12M
13M
20M
22N
5N
10N
11N
12N
13N
14N
21N
23P
11P
13P
20P
22R
3R
5R
21R
23T
4T
20
T22
V3
AC
23V
20W
6W
7W
10
W1
4W
18
W2
2Y
8A
A3
AA
8A
A12
AA
16A
A20
AB
8A
C1
AC
8
USB_PP0USB_PP1USB_PP2USB_PP3USB_PP4USB_PP5USB_PN#0USB_PN#1USB_PN#2USB_PN#3USB_PN#4USB_PN#5
USB_OC#0USB_OC#1USB_OC#2USB_OC#3USB_OC#4USB_OC#5
USB_LEDA#0/GPIO32USB_LEDA#1/GPIO33USB_LEDA#2/GPIO34USB_LEDA#3/GPIO35USB_LEDA#4/GPIO36USB_LEDA#5/GPIO37USB_LEDG#0/GPIO38USB_LEDG#1/GPIO39USB_LEDG#2/GPIO40USB_LEDG#3/GPIO41USB_LEDG#4/GPIO42USB_LEDG#5/GPIO43
USB_RBIAS
IDE_PDCS1#IDE_PDCS3#IDE_SDCS1#IDE_SDCS3#
IDE_PDA0IDE_PDA1IDE_PDA2IDE_SDA0IDE_SDA1IDE_SDA2
IDE_PDD0IDE_PDD1IDE_PDD2IDE_PDD3IDE_PDD4IDE_PDD5IDE_PDD6IDE_PDD7IDE_PDD8IDE_PDD9
IDE_PDD10IDE_PDD11IDE_PDD12IDE_PDD13IDE_PDD14IDE_PDD15
IDE_SDD0IDE_SDD1IDE_SDD2IDE_SDD3IDE_SDD4IDE_SDD5IDE_SDD6IDE_SDD7IDE_SDD8IDE_SDD9
IDE_SDD10IDE_SDD11IDE_SDD12IDE_SDD13IDE_SDD14IDE_SDD15
IDE_PDDACK#IDE_SDDACK#IDE_PDDREQIDE_SDDREQ
IDE_PDIOR#IDE_SDIOR#
IDE_PDIOW#IDE_SDIOW#IDE_PIORDYIDE_SIORDY
SPKR
VC
C_S
US
0V
CC
_SU
S1
VC
C_S
US
2V
CC
_SU
S3
VC
C_S
US
4V
CC
_SU
S5
VC
C_U
SB
0/V
CC
_SU
S6
VC
C_U
SB
1/V
CC
_SU
S7
VC
C_A
UX
0/V
CC
LAN
1_8
VC
C_A
UX
1/V
CC
LAN
1_8
VC
C_A
UX
2/V
CC
LAN
1_8
VC
C_R
TC
VC
C5R
EF
1V
CC
5RE
F2
VC
C5R
EF
SU
S1
VC
C5R
EF
SU
S2
VC
CP
AU
X0/
VC
CLA
N3_
3V
CC
PA
UX
1/V
CC
LAN
3_3
VC
CP
CP
U0
VC
CP
CP
U1
VC
CP
CP
U2
VC
CU
SB
BG
/VC
C_S
US
8
VC
CU
SB
PLL
/VC
C_S
US
9
N/C
0N
/C1
N/C
2N
/C3
N/C
4
VS
S10
2V
SS
103
VC
CP
PC
I0V
CC
PP
CI1
VC
CP
PC
I2V
CC
PP
CI3
VC
CP
PC
I4V
CC
PP
CI5
VC
CP
PC
I6V
CC
PP
CI7
VC
CP
0V
CC
P1
VC
CP
IDE
0V
CC
PID
E1
VC
CP
IDE
2V
CC
PID
E3
VC
CP
IDE
4
VC
CP
HL0
VC
CP
HL1
VC
CP
HL2
VC
CP
HL3
VCCA
VCCPSUS3/VCCPUSB0VCCPSUS4/VCCPUSB1VCCPSUS5/VCCPUSB2
VCCPSUS0VCCPSUS1VCCPSUS2
VC
CC
OR
E0
VC
CC
OR
E1
VC
CC
OR
E2
VC
CC
OR
E3
VC
CC
OR
E4
VC
CC
OR
E5
VC
CC
OR
E6
VS
S35
VS
S36
VS
S37
VS
S38
VS
S39
VS
S40
VS
S41
VS
S42
VS
S43
VS
S44
VS
S45
VS
S46
VS
S47
VS
S48
VS
S49
VS
S50
VS
S51
VS
S52
VS
S53
VS
S54
VS
S55
VS
S56
VS
S57
VS
S58
VS
S59
VS
S60
VS
S61
VS
S62
VS
S63
VS
S64
VS
S65
VS
S66
VS
S67
VS
S68
VS
S69
VS
S70
VS
S71
VS
S72
VS
S73
VS
S74
VS
S75
VS
S76
VS
S77
VS
S78
VS
S79
VS
S80
VS
S81
VS
S82
VS
S83
VS
S84
VS
S85
VS
S86
VS
S87
VS
S88
VS
S89
VS
S90
VS
S91
VS
S92
VS
S93
VS
S94
VS
S95
VS
S96
VS
S97
VS
S98
VS
S99
VS
S10
0V
SS
101
U21
@74AHCT1G125GW
24
13
5
R330
1K_0402
12
R209 0_04021 2
R331
@10K_0402
12
R327
10K_0402
12
R332
@10K_0402
12
R326
10K_0402
12
C398.1UF_0402
12
R226
1K_0402
1 2
R205 0_04021 2
PDDACK# <19>
SDIORDY <19>
PDA1 <19>
SDCS3# <19>
AC_VID2<6>SDD[0..15] <19>
PDIORDY <19>
AC_VID4<6>
PDA0 <19>
PDD[0..15] <19>
SDCS1# <19>
AC_VID1<6>
PDA2 <19>
AC_VID0<6>
PDIOW# <19>
PDCS1# <19>
SDDREQ <19>
PDCS3# <19>
SDIOR# <19>
PDDREQ <19>
SDA1 <19>
SDIOW# <19>
SDA2 <19>
SDDACK# <19>
AC_VID3<6>
PDIOR# <19>
SDA0 <19>
ICH_SPKR<24>
ICH_M_SEN#<18>
ACIN<28,33,35>
USBP2-<30>USBP2+<30>
USBP0+<30>USBP0-<30>
EC_FLASH#<28>
OVCUR#2<30>
OVCUR#0<30>
SIDERST#<19>
PIDERST#<19>
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��
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
����������� 0.1
*�+������� �(��%��"� ����&(
18 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
+3VS +3VS
+3VS
+3VS +3VS
+3VS
+3VALW
+3VS
+3VALW
+3VS
+CPU_CORE
+1.8VS
VCC1.8SUS
+3VS
+3VS
+RTCVCC
+3V
VCCPSUS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R250 10K_04021 2
R252 10K_04021 2
C434.1UF_0402
12
+C4401UF
12
C453.1UF_0402
12
C41247PF_0402
12
C51247PF_0402
12
C49947PF_0402
12
C416.1UF_0402
12
+C53322UF_10V_1206
12
C505.1UF_0402
12
C504.1UF_0402
12
C459.1UF_0402
12
C503.1UF_0402
12
C527.1UF_0402
12
+C40622UF_10V_1206
12
C423.1UF_0402
12
C54147PF_0402
12
C460.1UF_0402
12
C421.1UF_0402
12
C52847PF_0402
12
C457.1UF_0402
12
C407.1UF_0402
12
C546.1UF_0402
12
C502.1UF_0402
12
C526.1UF_0402
12
+C545
22UF_10V_1206
12
C524.1UF_0402
12
C537.1UF_0402
12
C538.1UF_0402
12
RP114
10P8R_8.2K
109876
12345
RP121
10P8R_8.2K
109876
12345
RP119
10P8R_8.2K
109876
12345
R367 @8.2K_04021 2
C487.1UF_0402
12
C45533PF_0402
12
C482.1UF_0402
12
C445.1UF_0402
12
C497.1UF_0402
12
C46633PF_0402
12
C432.1UF_0402
12
+C458100UF_D2_6.3V
12
C519.1UF_0402
12
C540.1UF_0402
12
C525.1UF_0402
12
R365 @8.2K_04021 2
R366 @8.2K_04021 2
R244 4.7K_04021 2R245 4.7K_04021 2
R224 10K_04021 2
R220 4.7K_04021 2R228 4.7K_04021 2
R311 10K_04021 2R375 10K_04021 2
C52210UF_6.3V_P
12
STOP#<16,20,21>
GNT#2<16,21>
FRAME#<16,20,21,27>
TRDY#<16,20,21,27>IRDY#<16,20,21> SERR# <16,20,21>
DEVSEL# <16,20,21>
PLOCK# <16,21>
PCI_REQA#<16>PCI_REQB#<16>
REQ#3 <16,20>REQ#2 <16,21>
REQ#1<16>REQ#0<16>
REQ#4 <16>
IRQ14<16,19>
IRQ15 <16,19>PIRQA# <15,16,21>PIRQB# <16,20>PIRQC# <16>
PIRQD#<16>
SMB_ALERT#<16>
ICH_RI#<16>
GNT#1<16>
SIRQ <16,21,26>
GNT#3<16,20>
PM_CLKRUN#<16,20,21,26>
SMLINK0<16>SMLINK1<16>
SMB_DATA<14,16>SMB_CLK<14,16>
GNT#0<16>
ICH_M_SEN#<17>
GNT#4<16>
SM_INTRUDER#<16>
PERR# <16,20,21>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
W=80mils
Placec caps. near FDD CONN.
CD-ROM Connector
Placea caps. near HDDCONN.
FDD Connector
HDD Connector
Placea caps. near CDROMCONN.
Correct HDD pin define ,pls update layout
0
Layout Note: +5VSHDD tracewidth 60 mil
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19 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
WDATA#
MTR0#FDDIR#
DISKCHG#INDEX#WRPRT#TRK0#
SDD11
SDD13
SDD6
SDD3
SDD1
SDD8
SDD14
RIRQ15
SDD7
RSDDACK#
SDD10
SDD0
SDD5
SDIORDY
SDD2SDD15SDDREQ
SDD9
PDIAG#
SDD4 SDD12
HDSEL#WGATE#
RDATA#
STEP#
SEC_CSEL
DRV0#
SDD[0..15]
PDD[0..15]
PDD8PDD6PDD5PDD4 PDD11PDD3 PDD12PDD2 PDD13PDD1 PDD14PDD0 PDD15
RPDDACK#
PDDREQ
PDIORDY
RIRQ14
PCSEL
PDD10PDD9
DRV0#ACT_LED#
PDD7
STEP#
WRPRT#
DRV0#
WGATE#
RDATA#
DISKCHG#
INDEX#
HDSEL#
WDATA#
TRK0#
FDDIR#
MTR0#3MODE#_11
3MODE#_13
3MODE#
3MODE#_11
3MODE#_13
PDIORDY
SDIORDY
PDDREQ
RPDDACK#
RIRQ14
SDDREQ
RSDDACK#
RIRQ15
PHDD_LED#
PHDD_LED#
SHDD_LED#SHDD_LED#
+5VS
+5VS
+5VS
+5VS
+5VS+5VS
+5VS
+5VSHDD
+5VSHDD
+5VS
+5VS
+5VS
+3VS
+3VS
+5VS
+5VSHDD
+5VS
+12VALW+5VS +5VSHDD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C110
1UF_25V_0805
12
C257
.1UF_0402
12
C136
.1UF_0402
12
C369
1000PF_0402
12
C520
.1UF_0402
12
C271 .1UF_04021 2
C134
1UF_25V_0805
12
C536
.1UF_0402
12
C523
1UF_25V_0805
12
C258
1000PF_0402
12
RP115
10P8R_1K
109876
12345
RP120
8P4R_1K
1 82 73 64 5
R139470_0402
12
C367
10UF_16V_1206
12
C529
10UF_16V_1206
12
C96
10UF_16V_12061
2
R188
470_0402
1 2
C135
.1UF_0402
1 2
R51@10K_0402
12
R198@10K_0402
12
R148 100K_04021 2
JP24
ACES 85201-2605-FDDCON
123456789
1011121314151617181920212223242526
+5VINDEX+5VDRIVE SELECT+5VDISK CHANGENCREADYDENSITY OUTMOTOR ONNCDIRECTIONDENSITY 2STEPGND / NCWRITE DATAGNDWRITE GATEGNDTRACK 00NC / GNDWRITE PROTECTGNDREAD DATAGNDSIDE 1 SELECT
R336 @0_04021 2
R335 0_04021 2
R193
4.7K_0402
1 2
R151
4.7K_0402
1 2
C116
10UF_16V_1206
12
C262
1000PF_0402
12
C263
.1UF_0402
12
C112
1UF_25V_0805
12
R192 22_04021 2
R191 22_04021 2
R189 @5.6K_04021 2
R152 22_04021 2
R149 22_04021 2
R155 @5.6K_04021 2
C365
33PF_0402
1 2
C277
33PF_0402
1 2
C366
10UF_16V_1206
12
U23A
74HCT08
1
23
14
7
R62100K_0402
12
JP18
HH99221-S6-HDDCON
1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 44
U23D
74HCT08
12
1311
JP15
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1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 50
R187100K_0402
12
C333 47PF_04021 2
C33747PF_0402
1 2
C280 47PF_04021 2
R176
100K_0402
12
C359.01UF_0402
12
R178150K
12
G
D
S
Q22
2N7002
2
13
Q23
SI2301DS
2
13
SDIOW#<17>SDIORDY<17>
SDCS1#<17>SDA0<17>SDA1<17>
INT_CD_R <23>
CD_AGND <23>
SIDERST#<17>
INT_CD_L<23>
SDA2 <17>
SDDREQ <17>SDIOR# <17>
SDCS3# <17>
SDD[0..15]<17>
PDDREQ<17>PDIOW#<17>PDIOR#<17>PDIORDY<17>
PDA1<17>PDA0<17>PDCS1#<17> PDCS3# <17>
PDA2 <17>
ACT_LED# <27>
INDEX#<26>
DRV0#<26>
DISKCHG#<26>
MTR0#<26>
FDDIR#<26>
WDATA#<26>
HDSEL#<26>
TRK0#<26>
STEP#<26>
WRPRT#<26>
WGATE#<26>
RDATA#<26>
3MODE#<26>
PIDERST#<17>
PDD[0..15]<17>
PDDACK#<17>
IRQ14<16,18>
IRQ15<16,18>
SDDACK#<17>
FDD_PRES#<29>
PIDEPWR<16>
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DSX630G H:1.2mm +-30ppm(20PF)
Compal Electronics, Inc.
Set Standard features
Set SMBus Mandatory
Set 16K EEPROM
3COM3C920 LAN CONTROLLER
Layout Note:H0022 Pls closely to RJ45 Conn.
Place closely to Lan chips
Place closely to Lan chips
Note1
Note1:Place this test point in the RAM door area
AT93C66 Pin6 (ORG)1=16 bit ; 0=8 bit
(LAN_ACT)
(LAN_100LINK)
(LAN_10LINK)
The cap please closely to H0022
10M LINK :Green LED100M LINK :Orange LEDActivity :Blink(Yellow LED)
R448 Closely AT93C86
FDC6320CGate 1: N-MOSGate 2: P-MOS
ADY13 LA-1271 0.1
3COM 3C920 LAN
20 37Monday, September 10, 2001
Title
Size Document Number Rev
Date: Sheet of
SOS6#
AD8
AD11AD12
SOS2#SOS3#
AD15
AD2
AD6
AD10
AD30
AD7
AD14
AD22
SOS7#
AD26
AD16
AD9
AD19
LAN_SOS5#
AD21AD20
AD24
AD31
SOS4#
AD1
AD3AD4AD5
AD17AD18
AD25
AD29
LAN_SOS1#
LAN_CRY1
AD0
AD13
AD27AD28
AD23
LAN_AD17
CLK_PCI_LAN
LAN_AD17AD17
LAN_TX+
LAN_RX+
LAN_CRY2
LAN_RJ45T+LAN_RJ45R+
LAN_RJ45T-
LAN_RJ45R-
LAN_100
LAN_10
LAN_100LAN_10
SOS2#SOS1#
SOS3#SOS4#
SOS5#
SOS6#
SOS7#
CLK_PCI_LAN
LAN_RX+LAN_RX-
LAN_TX+LAN_TX-
LAN_EESEL
LAN_DFRMEELAN_DTOEE
LAN_P1
LAN_P1
LAN_RX-
LAN_TX-
LAN_EECLK
LAN_DTOEE
LAN_DFRMEE
LAN_EECLK
LAN_RST#
LAN_RST#
LAN_SOS5#
LAN_SOS1#
+3VASB +3VALW+3RX_PWR
+3TX_PWR+3TX_PWR+3VS
+3VASB+3RX_PWR
+3RX_PWR+3VASB
+3VASB
+3VASB+3VASB
+3VASB
+3V
+3VASB
+3VASB
+3VASB
L43 @BLM21A601SPT12
L44 BLM11A121S12
L42 BLM11A121S12
C130
.01UF_0402
12
C2492.2UF_16V_0805
C351
2.2UF_16V_0805
C273
2.2UF_16V_0805
R48 10K_04021 2
R49 10K_04021 2
C34633PF_0402
12
Y1
XTAL25MHZ
12
R50 10K_0402
1 2
C344
.01UF_0402
12
C34733PF_0402
12
R170
10K_0402
12
C343
1UF
12
R53 10K_04021 2
R54
10K_04021 2
R12375_1%
12
R10975_1%
12
R12275_1%
12
R11275_1%
12
C227
@1000PF_1206_2KV 12
C211
1000PF_1206_2KV12
C327
.01UF_0402
12
C335
.01UF_0402
12
C341
.01UF_0402
12
C272
.01UF_0402
12
C274
.01UF_0402
12
C125
.01UF_0402
12
C129
.01UF_0402
12
C345
.01UF_0402
12
C354
.01UF_0402
12
C261
.01UF_0402
12
C259
.01UF_0402
12
C126
.01UF_0402
12
C350
.01UF_0402
12
C349
.01UF_0402
12
C255
.01UF_0402
12
C256
.01UF_0402
12
R17311.5K_1%
12
U17
3C920-V3
B11D11C11B12A12C12B13A14C13E11B14E12D13F11E13E14J12J13K11L12K12K13L11L13N14N13P14P12M11N12P11N11
D12F12H13M13
N10
M14
H14
D14
A13
D2
J2 A10
A7
E2
F2
H2
P1
P7
N8
K14
A8
L1 N2
P3
K2
P5
M6
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6 J7 J8 J9
M3L3L4K3F4C2B1
K1
M2
M7
P10
L14
C14
A11
G14
D1
J1 B10
A6
E1
G1
H1
P9
J14
B8
P2
N3
N1
N5
N7
M1
M4
G12M12
L9N9M9L10J11H11G13H12F14G11F13M8
M10
A1C3G3
C10D10
L8
B7C7B6D6C6C5A5B5
A4D5B4C4A3A2
C1D3E4E3
F3G4
H3H4J4J3K4
D7B3D4B2
D9A9C8D8
N6P6
N4P4
L5
M5L6
L7C9B9
F1
G2
L2P8P13
AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
CBE#0CBE#1CBE#2CBE#3
VS
SP
CI1
VS
SP
CI2
VS
SP
CI3
VS
SP
CI4
VS
SP
CI5
VS
SIO
1V
SS
IO2
VS
SIO
3V
SS
IO4
VS
SX
1V
SS
X2
VS
SX
3V
SS
X4
VS
SX
5V
SS
X6
VS
SX
7V
SS
X8
VS
SX
9
VS
SR
X1
VS
SR
X2
VS
SR
X3
VS
ST
X1
VS
ST
X2
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
SOS1#SOS2# / TXCLKSOS3# / TXENSOS4# / CRSSOS5# / RXOESOS6# / RXCLKSOS7# / MDCLK
MA
INP
5A
UX
5PN
AU
XP
VD
DP
CI1
VD
DP
CI2
VD
DP
CI3
VD
DP
CI4
VD
DP
CI5
VD
DIO
1V
DD
IO2
VD
DIO
3V
DD
IO4
VD
DX
1V
DD
X2
VD
DX
3V
DD
X4
VD
DX
5V
DD
X7
VD
DR
X1
VD
DR
X2
VD
DR
X3
VD
DT
X1
VD
DT
X2
PM
E
VD
DLV
DE
TPARIDSELINTA#RST#GNT#REQ#FRAME#IRDY#TRDY#DEVSEL#STOP#PERR#SERR#PME#CLKRUN#
SMBDATASMBCLKSMBCS#
WPOUTGRST#
PCICLK
LD0 / POR0LD1 / POR1LD2 / POR2
LD3LD4 / POR4
LD5LD6 / POR6
LD7
LA0LA1
LA2 / POR10LA3LA4LA5
RXD0 / LA6RXD1 / LA7RXD2 / LA8RXD3 / LA9
RXER / LA10RXDV / LA11
TXD0 / LA12TXD1 / LA13TXD2 / LA14TXD3 / LA15COL / LA16
ROMCS#MEMR#
MEMW#MDIO
EESELEECLK / ACT
DTOEE / 100LNKDFRAMEE / 10LNK
TXOPTXON
RXIPRXIN
TXCT (NC)
REF100REF10
MEDTESTGLBTEST#PHYTEST#
X25HI
X25L0
NC3NC5NC6
R1721.62K_1%
12
R1711.91K_1%
12
C352
.01UF_0402
12
C353
.1UF_0402
12
RP111
@8P4R_10K
1 82 73 64 5 R163 @10K_0402
1 2
R167 @10K_04021 2
R168 @10K_04021 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C268@10PF_0402
R147@33_0402
12
R120
0_0402
1 2
L41 68nH12
R153
61.9_1%_0805
12
U14
Pulse-H0022
123
678 9
1011
141516RD+
RD-CT
CTTD+TD- TX-
TX+CT
CTRX-RX+
R158
56.2_1%_0805
12
C336
.1UF_0402
12
R161
56.2_1%_0805
12
C242
4.7PF_NPO
1 2
R154
61.9_1%_0805
12
L20 BLM21A601SPT12
TP1
1
R135
10K_0402
12
U16
AT93C86-10SC2.7
1234
8765
CSSKDIDO
VCCNC
NC/ORGGND
R128
200_0402
12
R133
10K_0402
12
Q17
FDC6320C
1
2
3 4
5
6G1
S2
G2 D2
S1
D1
Q15
FDC6320C
1
2
3 4
5
6G1
S2
G2 D2
S1
D1
R136
200_0402
12
R140
200_0402
12
JP9
JM36113-L5H7
2
1
3
4
5
6
7
8
13 14
12 11 10 9
PR1-
PR1+
PR2+
PR3+
PR3-
PR2-
PR4+
PR4- SH
LD1
SH
LD2
LED
_GR
EE
N
LE
D_O
RA
NG
E
LD
E_Y
ELLO
W+
LD
E_Y
ELLO
W-
R141
100_04021 2
D11 RB751V21
R162 10K_04021 2
R46 @0_04021 2
R159 10K_04021 2
D5 RB751V21
D12 RB751V21
R52 10K_04021 2
LAN_PME#<29>
AD[0..31]<16,21,27>
FRAME#<16,18,21,27>
DEVSEL#<16,18,21>
PERR#<16,18,21>
PCIRST#<5,8,15,16,21,26,27,28>
IRDY#<16,18,21>
C/BE#0<16,21,27>
C/BE#2<16,21,27>
PIRQB#<16,18>
C/BE#3<16,21,27>
SERR#<16,18,21>
PAR<16,21>
GNT#3<16,18>REQ#3<16,18>
STOP#<16,18,21>
TRDY#<16,18,21,27>
C/BE#1<16,21,27>
CLK_PCI_LAN<14>
PM_CLKRUN#<16,18,21,26>
LAN_DISABLE#<28>
SOS1#<29>
SOS5#<29>
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A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
ADY13 LA-1271 0.1
PCMCIA controller OZ6912
21 37Monday, September 10, 2001
Compal Electronics, Ltd.Title
Size Document Number Rev
Date: Sheet of
S1_A[0..25]
S1_D[0..15]
S1_BVD1
S1_A23
S1_IOWR#
S1_INPACK#
S1_A15
S1_WE#
S1_A24
S1_A11
PCM_SPK#
S1_D1
S1_A10
S1_D4
S1_D0
S1_A3
S1_A22S1_A21
S1_CE2#
S1_RDY#
S1_A4
S1_A25
S1_A14
S1_A13
S1_CD1#
S1_D2
S1_CD2#
S1_A17
S1_D7
S1_D6
S1_D5S1_D12
S1_D10
S1_VS1
S1_A5
S1_A7
S1_A12
S1_A20
S1_A1
S1_RST
S1_A6
PCIRST#
S1_OE#
S1_D13
S1_D3
S1_D8
S1_A2
S1_D11
S1_D14
S1_BVD2
S1_A0
S1_A19
S1_A8S1_CE1#
S1_D15
S1_D9
S1_WAIT#
S1_REG#
S1_VS2
S1_A9S1_IORD#
S1_WP
CLK_PCI_PCM
AD26
AD5
AD29
AD10
AD24
AD18
AD3
AD22
AD14
AD30
AD6
AD21
AD28
AD16
AD19
AD7
AD31
AD9AD8
AD12
AD27
AD15
AD13
AD4
AD25
AD20
AD23
AD17
AD11
AD2AD1AD0
AD[0..31]
AD20
PCM_RI#
S1_A18
S1_A16
S1_VCC
+3VALW+3VS
+3VS
+3VS+3VS
R166 100_04021 2
R165@33_0402
12
C342
@22PF_0402
12
C247
.1UF_0402
12
C270
.1UF_0402
12
C265.1UF_0402
1 2
D10
RB751V
21
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R131 10K_04021 2
C339
.1UF_0402
12
C275
.1UF_0402
12
C246
.1UF_0402
12
C245
.1UF_0402
12
C340
.1UF_0402
12
C278
.1UF_0402
12
PQFP 14422.2 X22.2 X1.60
U18
OZ6912
12
345
6
789
1011
12
13
14
151617
18
19
20
212
2
23242526
27
2829
30
313233343536
37
38394041
42
43
44
454647
48
49
50
51525354555657
58
59
6061
62
63
6465
66
676869
70
71
72
73
74
75
76
77
78
79
8081
8283
84
85
86
87
88
89
90
9192
93
94
95
9697
98
99
10
0
101
10
2
103
104105
106
107
108
109110111
112
113
11
4
115116
117
118
119
120121
12
2
123
124
125
12
6
127128129
13
0
131
132
133
134
135136
137
13
8
139140141142
14
3
144
PCIREQ#PCIGNT#
AD31AD30AD29
GN
D
AD28AD27AD26AD25AD24
C/BE3#
IDSEL
VC
C
AD23AD22AD21
VC
CP
AD20
PCIRST#
PCIPCLKG
ND
AD19AD18AD17AD16
C/BE2#
PCIFRAME#PCIIRDY#
VC
CP
PCITRDY#PCIDEVSEL#PCISTOP#PCIPERR#PCISERR#PCIPAR
C/BE1#
AD15AD14AD13AD12
GN
D
AD11
VC
CP
AD10AD9AD8
C/BE0#
AD7
VC
CP
AD6AD5AD4AD3AD2AD1AD0
GN
DRI_OUT#/PME#
MF0MF1
SPKROUT
VC
CI
MF2MF3
G_RST#
MF4MF5MF6
SUSPEND#
VP
PD
0V
PP
D1
VC
CD
0#
VC
CD
1#
CCD1#/CD1#
CAD0/D3
CAD2/D11
GN
D
CAD1/D4
CAD4/D12CAD3/D5
CAD6/D13CAD5/D6
RS
VD
/D1
4
CAD7/D7
VC
C
CAD8/D15
CCBE0#/CE1#
CAD9/A10
VC
CC
B
CAD10/CE2#CAD11/OE#
CAD13/IORD#
GN
D
CAD12/A11
CAD15/IOWR#CAD14/A9
CAD16/A17
CCBE1#/A8
RS
VD
/A1
8
CPAR/A13
VC
C
CBLOCK#/A19
CPERR#/A14CSTOP#/A20
CGNT#/WE#
CDEVSEL#/A21
CCCLK/A16
CTRDY#/A22CIRDY#/A15
CFRAME#/A23
CCBE2#/A12
CAD17/A24
GN
D
CAD18/A7CAD19/A25
CVS2/VS2#
CAD20/A6
CRST#/RESET
CAD21/A5CAD22/A4
VC
C
CREQ#/INPACK#
CAD23/A3
CCBE3#/REG#
VC
CC
B
CAD24/A2CAD25/A1CAD26/A0
GN
D CVS1/VS1#
CINT#/READY
CSERR#/WAIT#
CAUDIO#/BVD2
CSTSCHNG/BVD1CCLKRUN#/WP
CCD2#/CD2#
VC
C
CAD27/D0CAD28/D8CAD29/D1CAD30/D9
RS
VD
/D2
CAD31/D10
R146 0_04021 2
C241
.1UF_0402
R138 33_04021 2
C266
.1UF_0402
12
C3344.7UF_10V_0805
12
SIRQ<16,18,26>
PM_CLKRUN#<16,18,20,26>
PCIRST#<5,8,15,16,20,26,27,28>
S1_WAIT# <22>
S1_INPACK# <22>S1_WE# <22>
S1_BVD1 <22>S1_WP <22>
S1_RDY# <22>
PCM_SPK# <24>S1_BVD2 <22>
S1_A[0..25] <22>
S1_CD2# <22>S1_CD1# <22>S1_VS2 <22>S1_VS1 <22>
S1_RST <22>
S1_CE2# <22>
S1_CE1# <22>
S1_REG# <22>
S1_OE# <22>
S1_IORD# <22>
S1_IOWR# <22>
VCCD0#<22>VCCD1#<22>
VPPD1<22>VPPD0<22>S1_D[0..15] <22>
PCM_SUSP#<28>
V_PRST#<22,28>
AD[0..31]<16,20,27>
CLK_PCI_PCM<14>
DEVSEL#<16,18,20>
FRAME#<16,18,20,27>IRDY#<16,18,20>TRDY#<16,18,20,27>
STOP#<16,18,20>
PAR<16,20>
PERR#<16,18,20>SERR#<16,18,20>
REQ#2<16,18>GNT#2<16,18>
PIRQA#<15,16,18>
PLOCK#<16,18>
C/BE#3<16,20,27>C/BE#2<16,20,27>C/BE#1<16,20,27>C/BE#0<16,20,27>
PCM_RI#<27>
PCM_PME#<29>
���
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��
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CardBus Socket
PCMCIA Power Controller
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22 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
S1_A23
S1_WP
S1_A[0..25]S1_D[0..15]
S1_VCCL
V_PRST#
S1_D3 S1_CD1#S1_D4S1_D5S1_D6S1_D7S1_CE1#S1_A10S1_OE#S1_A11S1_A9S1_A8S1_A13S1_A14S1_WE#S1_RDY#
S1_A16S1_A15S1_A12S1_A7S1_A6S1_A5S1_A4S1_A3S1_A2S1_A1S1_A0S1_D0S1_D1S1_D2S1_WP
S1_D11S1_D12S1_D13S1_D14S1_D15S1_CE2#S1_VS1S1_IORD#S1_IOWR#S1_A17S1_A18S1_A19S1_A20S1_A21
S1_A22S1_A23S1_A24S1_A25S1_VS2S1_RSTS1_WAIT#S1_INPACK#S1_REG#S1_BVD2S1_BVD1S1_D8S1_D9S1_D10S1_CD2#
S1_VCCL S1_VCCL
S1_VPP
S1_VCC
S1_VCC
+5VALW
+3VALW
S1_VCC
S1_VPP
+3VALW +5VALW
+12VALW
S1_VPP
S1_VPP S1_VPPS1_VCC
C248
.01UF_0402
12
C244
.1UF_0402
12
+C254
4.7UF_25V_1206
C243
10UF_10V_1206
12R144 22K_0402
1 2
R134 22K_04021 2
C358
.1UF_0402
C281
4.7UF_10V_0805
12
C283
.1UF_0402
C357
.1UF_0402
C282
.1UF_0402
C363
10UF_10V_1206
12
C356
10UF_10V_1206
12
U19
TPS2211
12
34
56
7
8
9
10
111213
1415
16
VCCD0VCCD1
3.3V3.3V
5V5V
GN
D
OC
12V
VPP
VCCVCCVCC
VPPD1VPPD0
SH
DN
C338
1UF_25V_0805
12
JP10
FOXCONN_1CA415M1-TA_68P
13579
11131517192123252729313335373941434547495153555759616365676971737577798183
24681012141618202224262830323436384042444648505254565860626466687072747678808284
135791113151719212325272931333537394143454749515355575961636567GNDGNDGNDGNDGNDGNDGNDGND
2468
101214161820222426283032343638404244464850525456586062646668
GNDGNDGNDGNDGNDGNDGNDGND
L40
FBM-11-160808-800LMT1 2
C2791000PF_0402
12
C236
1000PF_0402
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
S1_D[0..15]<21>S1_A[0..25]<21>
VCCD0# <21>VCCD1# <21>VPPD0 <21>VPPD1 <21>
S1_CD1# <21>
S1_CE1#<21>S1_CE2# <21>
S1_OE#<21> S1_VS1 <21>S1_IORD# <21>S1_IOWR# <21>
S1_WE#<21>S1_RDY#<21>
S1_VS2 <21>S1_RST <21>S1_WAIT# <21>S1_INPACK# <21>S1_REG# <21>S1_BVD2 <21>S1_BVD1 <21>
S1_CD2# <21>S1_WP<21>
V_PRST# <21,28>
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A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
W=40Mil
reserve for AC97 coedc using only
short the digital ground and analong ground
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23 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
CD_R_R
CD_GNA
CD_L_R
MDMIC
LINEL
LINER
CD_GNA
MONO_IN
MDSPK
VDDA
VDDA
+3VS
VDDC
AVDD_AC97
+5VALW+12VALW
+5VAU
+5VALW
VDDA
VDDA+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C376
@.1UF_0402
12
C379
@4.7UF_10V_0805
12
R235 @10K_040212
L49
HB-1M2012-121JT
1 2
C433 1000PF_04021 2
R260 0_08051 2
R233@100K_0402
1 2
+C426
@4.7U_25V_1206
C411
.1UF_0402
12
R306 6.8K_1%12
R287 6.8K_1%12
R255 47_04021 2
C430 1000PF_04021 2
R278 1K_040212
C420
.1UF_0402
12
R2793.3K_0402
12
C4101000PF_04021 2
C436
4.7UF_10V_0805
12
R254 22_04021 2
C4464.7UF_10V_0805
12
C401 @1000PF_04021 2
Y3
24.576 MHz
C462 2.2UF_16V_08051 2
U28
STAC9700
14
15
17
16
23
24
18
20
19
21
22
13
12
35
36
37
11
10
6
5
8
2
3
29
30
28
27
1 925 38
32
46
47
48
47
39
41
3133344344
45
402642
AUX_L
AUX_R
VIDEO_R
VIDEO_L
LIN_IN_L
LIN_IN_R
CD_L
CD_R
CD_GNA
MIC1
MIC2
PHONE
PC_BEEP
LINE_OUT_L
LINE_OUT_R
MONO_OUT
RESET#
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
XTL_IN
XTL_OUT
AFLT1
AFLT2
VREFOUT
REFFLT
VC
C
VC
C
AV
CC
AV
CC
FLT3D
ID1#
EAPD#
S/PDIF_OUT
GNDGND
HP_OUT_L
HP_OUT_R
BPCFGFLTI
FLTONCNC
ID0#
NCAGNDAGND
R238 @10K_040212
C427@1UF_25V_0805
12
C461 1UF_25V_08051 2
C405 @1000PF_04021 2
C404 @1000PF_04021 2
C419
@1000PF_0402
12
R286 6.8K_1%12
C425 22PF_0402
R258@100K_0402
12
C417
@.047UF
12
C429 22PF_0402
C3991000PF_040212
R288 6.8K_1%12
R2903.3K_0402
12
C463 1UF_25V_08051 2
C409@1UF_25V_08051 2
C451
2700PF
12
R26947K_0402
1 2
R2684.7K_0402
12
C447 1UF_25V_08051 2
C431@15PF_0402
D28@AS2431L
13
2
C507 @68PF12
+
-
U32A
@LM358
3
21
84
L51
@BLM21A601SPT12
C494
@.1UF_04021 2
[email protected]_0402
12
C496
@.1UF_0402
12
@5.1KR323
12
@5.11K_0.5%R3021 2
@100K_0402
R3341 2
@2.4KR317
12
@5.11K_0.5%
R3041 2
@442_1%
R3051 2
G
D
S
Q30@SI2306DS
2
13G
D
S Q35@2N7002
2
13
@0_0402
R3001 2
C486 @220PF12
C485
@.1UF_0402
12
C518
.1UF_0402
12
C207
.1UF_0402
12
C517
@4.7UF_10V_0805
12
C516
4.7UF_10V_0805
12
C513
.01UF_0402
12
C448
.1UF_0402
12
C443
.1UF_0402
12
C435
.1UF_0402
12
28.7K_1%
R3551 2
10K_1%
R368
12
U34
SI9182DH-AD
4
8
5
3
6
7 1
2
VIN
ON/OFF#
VOUT
GND
SENSE
ERROR CNOISE
DELAY
C472
2200PF
12
C452 .1UF_04021 2
C4241UF_25V_0805
12
C437
1UF_25V_0805
12
C438
.1UF_0402
12
C414
.1UF_0402
12
C465 1UF_25V_08051 2
R277 @1K_040212
INT_CD_L<19>
INT_CD_R<19>
MD_SPK<25>
IAC_SDATAO<16,25>
LEFT <24>
IAC_BITCLK <16,25>
SDATA_IN0 <16>
IAC_SYNC<16,25>
CD_AGND<19>
MD_MIC <25>
RIGHT <24>
MONO_IN<24>
SUSP <31>
SUSP#<27,28,31,36,37>
MICIN<24>
AC97_RST#<16,25>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+3V POWER
+5V POWER
Speaker Connector
W=40mils
LINE OUT
EXT. MIC
10 mils trace
����������� 0.1
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24 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
LEFT
RIGHT
MONO_IN
INTSPK_R-
INTSPK_L+
INTSPK_R+
INTSPK_L-
INTSPK_L+INTSPK_L-
LEFT
RIGHT
INTSPK_R+INTSPK_R-
INTSPK_L+
INTSPK_R+
INTSPK_L+
INTSPK_R+
OPBPASS
PR_LEFT
INTSPK_R+
INTSPK_L+
PR_RIGHT
EXTMIC
BIAS
EXT_MICMICSEL
MIC-
VBIAS
EXTRMIC
MIC_IN
MIC+
MICSEL
PR
NBA_PLUG
PL
NBA_PLUG
OP_SHUT
OP_SHUT
+3VS
+5VAMP
+5VSVDDA
VDDA
VDDA
+3VS
+5VALW
VDDA
VDDA
VDDA
VDDA
C375 .01UF_04021 2
C374 .01UF_04021 2
C391
.1UF_0402
12
C390
.1UF_0402
12
R285100K_0402
12
C464
1UF_25V_0805
1 2
R324
10K_0402
1 2
R320100K_0402
12
C377 1UF_25V_08051 2
C378 1UF_25V_08051 2
L47
@BLM21A05_08051 2
JP17
Speaker Conn.
1234
1234
C3944.7UF_10V_0805
12
R20150K1 2
R20750K1 2
R202150K1 2
R211100K1 2
R21075K1 2
R206150K1 2
R212100K1 2
R21375K1 2
C3894.7UF_10V_0805
12
C392
.1UF_0402
12
C17147PF_0402
12
R230100K
C16747PF_0402
12
+
C372220UF_10V_D
1 2
+
C371220UF_10V_D
1 2
R299
2K_0402
1 2
R291
2K_0402
1 2
R310
2K_0402
1 2 C469
@.1UF_0402
1 2
C473
1UF_25V_0805
1 2
C490
1UF_25V_0805
1 2
C498.1UF_0402
12
Q262SC2411EK
23
1
R319100K_0402
12
C483
1UF_25V_0805
1 2
R274
@10K_0402
12
D24
1SS355
21
C194
47PF_0402
12
C493
.1UF_0402
1 2U33
TC7SH14
1
2
34
5NC
A
GNDY
VCC
L37 BLM11A121S1 2
L36 BLM11A121S1 2
U23B
74HCT08
4
56
L46
BLM21A05_08051 2
R315
100K
12
L38 BLM11A121S1 2
C475
.22UF_0805
1 2
R3142K_0402
R2962K_0402
R3131K_0402
R2891K_0402
C495
1UF_25V_0805
12
C4891UF_25V_0805
12
C474
.22UF_0805
1 2
L39 BLM11A121S1 2
JP7
JA6333L-100
12
3
4
5
6
C189
47PF_0402
12
C370
.22UF_0805
1 2
C479
.1UF_0402
1 2
U30
CMAMP110
1
2
3
4
5
6
7
8SEL
OUT
BIAS
VS
UP
INT_MIC+
INT_MIC-
GN
D
EXT_MIC
R203
2K_0402
R2041K_0402
C373
1UF_25V_0805
12
C456
.22UF_0805
1 2
C467
@.22UF_0805
1 2
R276
0
R271 @1K_0402
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
JP6
JA6333L-100
12
3
4
5
6
U24
TPA0202
1121324
7 18118
14
16
20
19
6
23172
9
10
3
15
22
5
21
4
GN
D/H
SG
ND
/HS
GN
D/H
SG
ND
/HS
LVD
DR
VD
DMUTEINSHUTDWSE/BTL#
HO/LINE#
RHPIN
RBYPASS
LBYPASS
NCNCNC
MUTEOUT
LOUT-
LOUT+
ROUT-
ROUT+
LHPIN
RLINEIN
LLINEIN
C169
47PF_0402
12
C188
47PF_0402
12
PCM_SPK#<21>
ICH_SPKR<17>
BEEP<29>
LEFT<23>
RIGHT<23>
MONO_IN <23>
MUTE<28>
INT_MIC- <30>
INT_MIC+ <30>
MICIN<23>
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1: Have primary CODEC on mother board
Pin 2 is NC for Pctel and connexant MDC modem
Pin 1 is NC for Pctel and connexant MDC modem
MDC Conn.
Screw HoleFiduial Mark
Spare Logic Gate
MDC Note
����������� 0.1
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25 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
+5VMDC
+3V
+3V+3VMDC
+5V
+3VMDC
+3V
+3VALW
+12VALW
C269
@.1UF_0402
12
C267
@1000PF_0402
12
C108
@.1UF_0402
12
R145 10K_04021 2
R45 @0_08051 2
R157@22_0402
12
C264.1UF_0402
12
R15622_0402
12
JP21
AMP 3-1473290-0
13579
111315
2321
1719
252729
24681012141618202224262830
MONO_OUT/PC_BEEPAGNDAUXA_RIGHTAUXA_LEFTCD_GNDCD_RIGHTCD_LEFTGND
AC97_SDATA_OUT3.3Vmain
3.3VauxGND
AC97_RESET#GNDAC97_MSTRCLK
AUDIO_PWDNMONO_PHONE
RESERVEDGND+5V
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDAC97_SYNC
AC97_SDATA_IN1AC97_SDATA_IN0
GNDAC97_BITCLK
R143 @0_08051 2
R150 0_08051 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
H5C315D126
1
H2C315D126
1
H1C315D126
1
H10O197X138D197X138N
1
H9S315D118
1
H6C315D126
1
H19C315D118
1
H3C315D157
1
H4C315D157
1
H27C256D157
1
H26C256D157
1
H7C315D157
1
H20C354D244
1
H21C354D244
1
H12O217X106D177X67
1
H13O217X106D177X67
1
H22O106X217D67X177
1
H16O106X217D67X177
1
H14C138D138N
1
M2S394D138
1
M7S276D110
1
M5S173D95
1
M6S173D95
1
H25C315D110
1
H17O106X217D67X177
1
H18O106X217D67X177
1
H23O106X217D67X177
1
H15S315D118
1
H11S315D118
1
M3S315D118
1
H8R256X315D138
1
FD1
FIDUCIAL MARK
1FD3
FIDUCIAL MARK
1FD2
FIDUCIAL MARK
1
FD6
FIDUCIAL MARK
1FD5
FIDUCIAL MARK
1
CF2
SMDC40M80
1CF1
SMDC40M80
1CF13
SMDC40M80
1CF17
SMDC40M80
1CF3
SMDC40M80
1
CF4
SMDC40M80
1CF12
SMDC40M80
1CF5
SMDC40M80
1CF14
SMDC40M80
1
CF8
SMDC40M80
1CF7
SMDC40M80
1CF10
SMDC40M80
1CF16
SMDC40M80
1
CF11
SMDC40M80
1
CF15
SMDC40M80
1
FD4
FIDUCIAL MARK
1
+
-
U32B
@LM358
5
67
84
M1C315D118
1
M4C315D118
1
M8S315D244
1
U36D
74LVC125
12 11
13
U36C
74LVC125
9 8
10
C109
@1000PF_0402
12
CF6
SMDC40M80
1CF9
SMDC40M80
1
C276
4.7UF_10V_P
12
H24C244D118
1
MD_SPK <23>
AC97_RST#<16,23>IAC_SDATAO<16,23>
MD_MIC<23>
IAC_BITCLK <16,23>
IAC_SYNC <16,23>SDATA_IN1 <16>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BASE ADDRESS CONFIGURATIONXBUS RESET CONFIGURATION
BADDR PULL-UP :4E
BADDR PULL-DOWN:2E
(DEFAULT)
XCNF0
XCNF1
Pin # 61
Signal Pin # Description
BADDR
TEST
XCNF[2:0]
61
58
90, 4, 59
BASE Address Selection
"0": 2E~2F (Default)
"1": 4E~4F
"0": Normal (Default)
"1": Test Mode
2 1 0 Function
x 0 0 No BIOS
x 0 1 Normal Mode. XRDY disabled
0 1 0 Latch Mode. XA12-19, XRDY enabled
1 1 0 Latch Mode. GPIO10~17,XRDY enabled
0 1 1 Latch Mode. XA12-19, XRDY disabled
1 1 1 Latch Mode. GPIO10~17,XRDY disabled
(default) * 1 ROM SOLUTION
IRQ8
����������� 0.1
� ��0�(���*-1��0� �9�7�
26 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
WRPRT#
INDEX#
LPTSLCTIN#
LPTSTB#
LPTINIT#
XIOCHRDY
XA3
DRV0#
LPTSLCT
LPTERR#LPTAFD#
XA1XA0
LPTPELPTBUSYLPTACK#
LPD4
XCNF2
LPD6LPD7
FDDIR#
3MODE#
XSTB0#
STEP#
LPD0
XD2
WGATE#
XD3
WDATA#
LPD2
LPD5
XD0XD1
XD5XD6
LPD3
XMEMR#
HDSEL#RDATA#
MTR0#
XD4
XA2
TRK0#
LPD1
XD7
XMEMW#
DTRA#
XA12XA13
XA16
TXDA
XMEMW#
XCNF2
XA17
XA14XA15
XA18
XIOR#XIOW#
LAD1LAD0
LPCSMI#SIRQ
LAD2LAD3
LFRAME#LDRQ#0
CLK_PCI_SIOLPC_RST#
CLK_14M_SIOCLK_PCI_SIO CLK_14M_SIO
DISKCHG#
LPC_RST#
+3VS
+3VS
+3VS
+3VS
+3VS+3VS
+3VS
+3VS
+3VS
+3VALW+3VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C481
@15PF_0402
12
C471
.1UF_0402
12
C439
1000PF_0402
12
PC87393
U31
PC87393F
15161718
89
12
67
11
1019
20
14 39 63 88
13 38 64 89
2122232425262728293031323334
5250484645444342
35363740414749515354
5556575859606162
7069686766
32110099989796
45737172
7475767778798081828384858687909192939495
LAD0LAD1LAD2LAD3
LCLKLRESET#LFRAME#
CLKRUN#/GPIO36LPCPD#LDRQ#
SERIRQSMI#/GPIO35
CLKIN
VD
DV
DD
VD
DV
DD
VS
SV
SS
VS
SV
SS
DSKCHG#HDSEL#RDATA#WP#TRK0#WGATE#WDATA#SETP#DIR#DR0#MTR0#INDEX#DENSELDRATE0/IRSL2
PD0/INDEX#PD1/TRK0#
PD2/WP#PD3/RDATA#
PD4/DSKCHG#PD5/MSEN0
PD6/DRATE0PD7/MSEN1
PNF/XRDYSLCT/WGATE#
PE/WDATA#BUSY_WAIT#/MTR1#
ACK#/DR1#SLIN#_ASTRB#/STEP#
INIT#/DIR#ERR#/HDSEL#
AFD#_DSTRB#/DENSELSTB#_WRITE#
DCD1#DSR1#
SIN1RTS1#/TEST
SOUT1/XCNF0CTS1#
DTR1#_BOUT1/BADDRRI1#
IRTXIRRX1
IRRX2_IRSL0IRSL1
IRSL3/PWUREQ#
XD0/GPIO00/JOYABTN1XD1/GPIO01/JOYBBTN1
XD2/GPIO02/JOYAYXD3/GPIO03/JOYBYXD4/GPIO04/JOYBXXD5/GPIO05/JOYAX
XD6/GPIO06/JOYBBTN0XD7/GPIO07/JOYABTN0
XWR#/XCNF1XRD#/GPIO34/WDO#
XIOWR#/XCS1#/MTR1#/DRATE0XIORD#/GPIO37/IRSL2/DR1#
XCS0#/DR1#/XDRY/GPIO25XA19/DCD2#/JOYABTN0/GPIO17XA18/GPIO16/JOYBBTN0/DSR2#XA17/GPIO15/JOYAX/SIN2XA16/GPIO14/JOYBX/RTS2#XA15/GPIO13/JOYBY/SOUT2XA14/GPIO12/JOYAY/CTS2#XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2XA12/GPIO10/JOYABTN1/RI2#XA11/GPIO33/XIOWR#/MDTXXA10/GPIO32/XIORD#/MDRXXA9/GPIO31/MTR1#/PIRQDXA8/GPIO30/PIRQCXA7/GPIO27/PIRQBXA6/GPIO26/PRIQA/XSTB2#XA5/XSTB1#/XCNF2XA4/GPIO24/XSTB0#XA3/GPIO23XA2/GPIO22XA1/GPIO21XA0/GPIO20
C442
.1UF_0402
12
C413
4.7UF_10V_0805
12
R303 @0_04021 2
R239 @10K_04021 2
R2924.7K_0402
12
R293 10K_04021 2
R262 @10K_04021 2
R282 10K_04021 2
R23610K_040212
R294 @10K_04021 2
R240 @10K_04021 2
R284@33_0402
12
RP1128P4R_10K
18
27
36
45
U38C74LVC14
5 6
714
R379 10K_04021 2
C542
.01UF_0402
12
U38D74LVC14
9 8
714
R28310_0402
12
C480
5PF_0402
12
XIOR#<28>XIOW#<28>
LPD0 <27>LPD1 <27>LPD2 <27>LPD3 <27>LPD4 <27>LPD5 <27>LPD6 <27>LPD7 <27>
LPTBUSY <27>
LPTSLCTIN# <27>
LPTSLCT <27>
LPTACK# <27>
LPTERR# <27>
LPTPE <27>
IRQ1<28>
MTR0#<19>
FDDIR#<19>DRV0#<19>
HDSEL#<19>
IRQ11<28>IRQ12<28>
XIOCHRDY <28>
WGATE#<19>WDATA#<19>
STEP#<19>
XA12<28>XA13<28>XA14<28>XA15<28>XA16<28>
XA18<28>XA17<28>
XA1<28>XA0<28>
XA3<28>XA2<28>
XMEMR# <28>XMEMW# <28>
XD0 <28>XD1 <28>XD2 <28>XD3 <28>XD4 <28>XD5 <28>XD6 <28>XD7 <28>
LAD2<16>LAD1<16>
LDRQ#0<16>
LAD3<16>
LAD0<16>
SIRQ<16,18,21>EC_SMI#<16,28>
XSTB0#<28>
3MODE#<19>
LPTSTB# <27>LPTAFD# <27>
LPTINIT# <27>
SUS_STAT#<15,16>
LFRAME#<16>
CLK_14M_SIO<14>
CLK_PCI_SIO<14>
PM_CLKRUN#<16,18,20,21>
WRPRT#<19>RDATA#<19>
TRK0#<19>
INDEX#<19>
DISKCHG#<19>
PCIRST#<5,8,15,16,20,21,27,28>
DCDA# <27>DSRA# <27>RXDA <27>
CTSA# <27>
RIA# <27>
RTSA# <27>TXDA <27>
DTRA# <27>
���
���
��
��
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
w=10mils
w=10mils
Parallel Port
4516
W=40milsW=40mils
PS2 CONN.
Touch Pad & Status LED Conn.
�'()*)'+,*-+� ��)+..*)-+/�
from cardbus
Reserved serial port for software ACPI debug
Debug PORT
ACPI Debug port
����������� 0.1
*1- 0� ��-#: �� %%5�"� �*�������� %%5
27 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
ACK#BUSYPE
LPTSTB#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
AFD/3M#ERR#PRNINIT#SLCTIN#
ACK#BUSYPESLCT
FD4FD5FD6FD7
FD7FD6FD5FD4
FD0
FD3
FD1FD2
PRNINIT#
AFD/3M#SLCT
SLCTIN#
ERR#
LPD[0..7]
FD3FD2FD1FD0
AFD/3M#FD0ERR#FD1PRNINIT#FD2SLCTIN#FD3
FD4
FD5
FD6
FD7
ACK#
BUSY
PE
SLCT
PWRPRN
KBD_DATA
PS2_DATA
PS2_CLK
KBD_CLK
TP_CLK
TP_DATA
CHARGE_LED#ACT_LED#PWR_LED#BATT_LED#
TP_CLK TP_DATA
ACT_LED#CHARGE_LED#
PWR_LED#BATT_LED#
RI1#DTR1#CTS1#TXD1
RTS1#RXD1DSR1#DCD1#
CTS1#RI1#
TXDA
DTRA#RTSA#
SUSP#
RXDA
CTSA#RIA#
DSRA#DCDA#
CLK_PCI_LPC
DTR1#RTS1#TXD1
RXD1DCD1#DSR1#
DCD1#TXD1
RTS1#RI1#
CTS1#DSR1#DTR1#RXD1
+5V_PRN
+5V_PRN
+5V_PRN
+5V_PRN
+5V_PRN
+5VS
+5V_PRN
+5VS KB_ASPS2KB_VCC
+5VS+5VS
+5VALW
+5V
+5VALW
+5VS
+3VS
RP2
10P8R_2.7K
109876
12345
RP1
10P8R_2.7K
109876
12345
R6733_0402
1 2
R682.7K_0402
12
CP13
8P4C_270PF
1 82 73 64 5
CP1
8P4C_270PF
1 82 73 64 5
CP12
8P4C_270PF
1 82 73 64 5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
C147
4.7UF_10V_0805
12
CP2
8P4C_270PF
1 82 73 64 5 C149
.1UF_0402
12
L30 01 2
L6 01 2
L24 01 2
L29 01 2
L7 01 2
L28 01 2
L27 01 2
L26 01 2
L25 01 2
L8 01 2
L9 01 2
L10 01 2
L2 01 2
L3 01 2
L4 01 2
L5 01 2
JP1
LPTCN-25-SUYIN
13251224112310229
218
207
196
185
174
163
152
141
D6
1SS355
2 1
C148
47PF_0402
1 2
JP5
KBD/PS2_6
33005A-06T1-01-PS2I16795326
5
6
3124
F1
POLYSWITCH_1.1A
U3
KBMF01SC6
123 4
56DATA IN
GNDCLK IN CLK OUT
VCCDATA OUT
L15FBM-11-451616-800T
1 2
C141UF_25V_0805
12
U2
KBMF01SC6
123 4
56DATA IN
GNDCLK IN CLK OUT
VCCDATA OUT
CP3
@8P4C_220PF
18273645
C128
@220PF
1 2
C127
@220PF
1 2
JP13
JST BM20B-SRDS-G
1 23 45 67 89 10
1214
111315 161719
1820
CP10@8P4C_270PF
1 82 73 64 5
CP11@8P4C_270PF1 82 73 64 5
C142
@.1UF_0402
1 2
C141
@.1UF_0402
12
[email protected]_0402
1 2
U6@MAX3243
3
26
22
2827
241
2
2325
9101145678
141312191817161520
21
V-
VC
C
FORCEOFF#
C1+V+
C1-C2+
C2-
FORCEONGND
TOUT1TOUT2TOUT3
RIN1RIN2RIN3RIN4RIN5
TIN1TIN2TIN3ROUT1ROUT2ROUT3ROUT4ROUT5ROUTB2
INVLD#
[email protected]_0402
1 2
R34520K_0402
12
D31
RB751V
21
C143
@.1UF_0402
1 2
R47@33_0402
12
C124@10PF_0402
JP23
AMP 5-175638-0
1 23 45 67 89 10
1214
111315 161719
1820
JP19
@E&T 2041-010-10
13579
246810
+++++
+++++
LPTACK#<26>
LPTBUSY<26>
LPTPE<26>
LPTSLCT<26>
LPTERR#<26>
LPTAFD#<26>
LPD[0..7]<26>
LPTSTB#<26>
LPTINIT#<26>
LPTSLCTIN#<26>
KBD_CLK<28>
KBD_DATA<28>
PS2_CLK<28>
PS2_DATA<28>
TP_DATA <28>TP_CLK<28>
ACT_LED#<19>CHARGE_LED#<29>
PWR_LED# <29>BATT_LED# <29>
CTSA#<26>
DSRA#<26>
TXDA<26>
RXDA<26>RIA#<26>
RTSA#<26>
DCDA#<26>
DTRA#<26>
SUSP#<23,28,31,36,37>
RING# <28>PCM_RI#<21>
AD9<16,20,21>
AD6<16,20,21>AD2<16,20,21>AD1<16,20,21>AD5<16,20,21>AD8<16,20,21>
C/BE#2<16,20,21>
C/BE#0 <16,20,21>AD4 <16,20,21>AD0 <16,20,21>AD3 <16,20,21>AD7 <16,20,21>C/BE#1 <16,20,21>C/BE#3 <16,20,21>
PCIRST# <5,8,15,16,20,21,26,28>FRAME#<16,18,20,21>TRDY# <16,18,20,21>
CLK_PCI_LPC <14>
LID_SW# <29,30>
���
���
��
��
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NC: 1,2,43,44,45,46,87,88,89,90,131,132,133,134,175,176
Pin 130 PU forZero Latch
IREF: Charger current controlADPREF: Adapter currentcontrol
LI/MH#
����������� 0.1
�93;
28 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
KBA[0..18]
ADB[0..7]
KSI[0..7]
KSO[0..15]
XA0XA1XA2XA3
XA12XA13XA14XA15XA16XA17XA18
XD0XD1XD2XD3XD4
XD7
XD4
XD0
XD5XD6
ECAGND
XD5
51RST
SMB_EC_CK1SMB_EC_DA1
CRY2
CRY1
KBA0KBA1KBA2KBA3KBA4KBA5KBA6KBA7KBA8KBA9KBA10KBA11KBA12KBA13KBA14KBA15KBA16KBA17KBA18
KBA18
ADB0
ADB0ADB1ADB2ADB3ADB4ADB5ADB6ADB7
ADB1ADB2ADB3ADB4ADB5ADB6ADB7
FWR#FRD#
FSEL#
KSI0KSI1KSI2KSI3KSI4KSI5KSI6KSI7
KSO0KSO1KSO2KSO3KSO4KSO5KSO6KSO7KSO8KSO9KSO10KSO11KSO12KSO13KSO14KSO15
KBD_DATAKBD_CLKPS2_DATAPS2_CLKTP_DATATP_CLK
FWR#
EC_THRM#
EC_ON
FSEL#KBA18
KBD_DATA
PS2_DATAPS2_CLK
FRD#
TP_DATATP_CLK
KBD_CLK
XD7XD6
XD2XD1
XD3
FWE#
KBA15KBA17
BKOFF#SELIO#
VBATT
BATT_CHGI
XD[0..7]
HMEMR#
G_RST#
ECAGNDBATT_TEMP
RCL#
RCL#G20
SMB_EC_DA1SMB_EC_CK1
G_RST#
G20
570_SMI#
570_SMI#
HMEMW#
ACOFF
PFAIL#
570_SMI#
PCM_SUSP#KSO17
BATT_TEMP
ECAGNDVBATT
BATT_CHGI ECAGND
ECAGNDBATT-OVP
KB_VCC
+5VS
+5VS
+5VS
+5VALW
+5VALW
+5VALW
+5VALW
+5VALW
+3VALW
+5VALW
+3VS
+5VALW
+5VS
+5VBIOS
+5VALW
+RTCVCC
+5VALW
+3VALW
+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
X1
32.768KHZ
RP113
10P8R_10K
109876
12345
L52BLM11A20
12
C478
.1UF_0402
1 2
R232
22M
1 2
R231
51K_040212
R380
100K_0402
1 2
R1300_0402
12
R12910K_0402
12
R386100K_0402
12
G
D S
Q402N7002
2
1 3RP117
8P4R_10K
1 82 73 64 5
G
DSQ272N7002
2
13
R343
100K
12
U29
7SH32
2
14
5
R381
100K_0402
1 2
G
DSQ282N7002
2
13
R256@0_0402
1 2
C484 .01UF_04021 2
R30910K_0402
12
D25
RB751V
2 1
R2724.7K_0402
12
R2754.7K_0402
12
R27310K_0402
12
D23
RB751V
2 1
L50
BLM11A201 2
C441
.1UF_0402
12
C444
1000PF_0402
12
RP116
8P4R_10K
1 82 73 64 5
C403
33PF_0402
12
C238
.1UF_0402
12
R26610K_0402
12
C400
10PF_0402
12
PC87570
U26
PC87570C4-176PIN
166167168169170171172173174
3456789
101112
1516171819202122
1314
158159157162163
164165
161
108
67 23
28
91
24 26 66 109
160
156155154153
2527
3635343332313029
56555453525150494847424140393837
575859606970
114115116117118119120121122123124125126127128129130135136
137138139140141142143144
145146147148149150151152
112
113
95969798
8182838485869394
616263646568
10410310210110099
7172737475767778
79
110107106
105
111
80 92
HA0HA1HA2HA3HA4HA5HA6HA7HA8HA9HA10HA11HA12HA13HA14HA15PA3/HA16PA4/HA17PE0/HA18
HD0HD1HD2HD3HD4HD5HD6HD7
HAENHIOCHRDYHIOR#HIOW#HMEMCS#/PA0HMEMRD#/PA1HMEMWR#/PA2
HMRHPWRON
VC
CV
CC
VC
CV
CC
VBAT
AV
CC
GN
DG
ND
GN
DG
ND
GN
D
IRQ1IRQ8#IRQ11IRQ12
32KX1/32CLKIN32KX2
KBSIN0KBSIN1KBSIN2KBSIN3KBSIN4KBSIN5KBSIN6KBSIN7
KBSOUT0KBSOUT1KBSOUT2KBSOUT3KBSOUT4KBSOUT5KBSOUT6KBSOUT7KBSOUT8KBSOUT9
KBSOUT10KBSOUT11KBSOUT12KBSOUT13KBSOUT14KBSOUT15
PSDAT1PSCLK1PSDAT2PSCLK2
PSDAT3/PC7PSCLK3/PC6
A0A1A2A3A4A5A6A7A8A9
A10A11A12
A13/BE0A14/BE1
A15/PG1/CBRDA16/PA5/FXBUSEN
A17/PA6A18/PE1/SHBM#
D0D1D2D3D4D5D6D7
D8/PF0D9/PF1
D10/PF2D11/PF3D12/PF4D13/PF5D14/PF6D15/PF7
WR0#
PG4/WR1#
DA0DA1DA2DA3
PD0/AD0PD1/AD1PD2/AD2PD3/AD3PD4/AD4PD5/AD5PD6/AD6PD7/AD7
PC0PC1PC2PC3/EXINT0PC4/EXINT11PC5/EXINT15
PH0/BST0/ENV0PH1/BST1/ENV1PH2/BST2/TRIS
PH3/PFSPH4/PLI
PH5/ISE#
PB0/RING#PB1/SCLPB2/SDAPB3/TAPB4/TB/EXINT10PB5/GA20PB6/HRSTO#PB7/SWIN
PFAIL#
PG0/SELIOPG2/CLK
PG3/SEL1#
HRMS/SEL0#
RD/HDEN
VR
EF
AG
ND
C449
.1UF_0402
12
R2641K_040212
U1539SF040
12111098765
272623254
282932
222431
1
1314151718192021
32
16
30
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16
CE#OE#WE#
VPP
D0D1D2D3D4D5D6D7
VCC
GND
A17
R25310K_0402
12
RP118
8P4R_10K
1 82 73 64 5
C501
.1UF_0402
12
R325 10K_040212
+ C239
10UF_10V_1206
12
C3971UF_25V_0805
1 2
C402
1000PF_0402
12
U43A
74HCT32
1
23
14
7
D26
RB751V
21
R261100K_0402
12
C488 .01UF_04021 2
C492 .01UF_04021 2
C477 .01UF_04021 2
XA1<26>XA0<26>
XA3<26>XA2<26>
XA12<26>XA13<26>XA14<26>XA15<26>XA16<26>
XA18<26>XA17<26>
XIOCHRDY<26>XIOR#<26>XIOW#<26>
TP_CLK <27>
KBD_CLK <27>
IRQ1<26>
IRQ12<26>
XSTB0#<26>
SLP_S3#<16>SLP_S5#<16>
SLP_S1#<14,16>
SMB_EC_CK1<5,7,15,29,33>SMB_EC_DA1<5,7,15,29,33>
ACIN <17,33,35>BKOFF# <15>
FSTCHG <34>
TP_DATA <27>
KBD_DATA <27>
SELIO# <29>
EC_ON <30>
KBA[0..18] <29>
ADB[0..7] <29>
KSI[0..7] <29,30>
KSO[0..15] <29>
SCI# <16>
XD0<26>XD1<26>
XD6<26>
XD2<26>
XD5<26>
XD3<26>
XD7<26>
XD4<26>
IRQ11<26>
KSO17 <30>
PS2_DATA <27>PS2_CLK <27>
EC_THRM# <16>
EC_HPOWON<7>
SCRLED#<30>NUMLED#<30>
RING#<27>
ON/OFF<30>
EC_FLASH# <17>
XD[0..7]<26>
XMEMW#<26>
XMEMR#<26>
CAPSLED#<30>
PCIRST#<5,8,15,16,20,21,26,27>V_PRST# <21,22>
MUTE <24>
EN_DFAN<7>
DAC_BRIG<15>
IREF<34>
KBRST#<16>
GATEA20<16>
EC_SMI# <16,26>
PCM_SUSP# <21>INVT_PWM<15>
ACOFF <34>FAN1_TACH<7>
SYSON <31,33,37>
LAN_DISABLE# <20>
BATT-OVP<34>
SUSP#<23,27,31,36,37> G_RST#
VR_ON <31,32>
BATT_TEMP<33>
FAN2_TACH<7>
EN_DFAN2<7>
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��
��
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EC I2C Bus Address:
NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
24C164: 1011xxx R/W#24C16: 1010xxx R/W#
Input PortOutput Port
INT_KBD CONN.
����������� 0.1
6��6<��%��*-1�=��� %%5�"��*10
29 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
ADB[0..7]
KSO[0..15]
KSI[0..7]
KBA[0..18]
ADB0ADB1ADB2ADB3ADB4ADB5ADB6ADB7
KBA3AA
SELIO# LARST#
KBA1
SELIO#
ADB6
ADB4ADB5
ADB0
ADB3ADB2
ADB7
ADB1
PCM_PME#
CC
PCM_PME#AACC
KBA2
SELIO#
ADB6
ADB4ADB5
ADB0
ADB3ADB2
ADB7
ADB1
DD
ADB0ADB1ADB2ADB3ADB4ADB5ADB6ADB7
KBA4BB
SELIO# LARST#
BBDD
KSO15
KSO7
KSO13KSO12KSO3KSO6
KSO8
KSO10
KSO2
KSO11KSO14
KSO4
KSI2KSO0KSI5KSI4
KS
O9
KS
I2
KS
I0
KS
I7
KS
O13
KS
O11
KS
O3
KS
O4
KS
I5
KS
O8
KS
O5
KS
O15
KS
O6
KS
O1
KS
I1
KS
O0
KS
O7
KS
O14
KS
I3KS
O12
KS
I4
KS
I6
KS
O2
KS
O10
KSI6KSO9
KSI1KSI7
KSO5KSI3
KSI0KSO1
+5VALW
+5VALW
+5VALW
+5VALW
+5VALW
+5VALW
+3V
+5VALW
+5VALW
+5VALW
+5VALW
+5VALW +5VALW
+5VALW
+5VALW
+3VS
+3VALW
+5VALW
+5VALW
+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R356 20K_04021 2
R358 100K_04021 2
R247100K_0402
12
RP123@8P4R_100K
18
27
36
45
RP125@8P4R_100K
18
27
36
45
RP124
8P4R_100K
1 82 73 64 5
R321@0_0402
12
R360100K_0402
1 2
R370100K_0402
1 2
R377100K_0402
1 2
U42
@7SH32
2
14
5
U40
74HCT273
24 57 68 9
13 1214 1517 1618 19
3
11
20
1
10
Q0D1 Q1D2 Q2D3 Q3D4 Q4D5 Q5D6 Q6D7 Q7
D0
CLK
VC
C
CLR GN
D
U25
NM24C16
12
56
8
34
7A0A1
SDASCL
VCC
A2GND
WC
U37
74HCT244
2 184 166 148 12
11 913 715 517 3
119
2010
1A1 1Y11A2 1Y21A3 1Y31A4 1Y42A1 2Y12A2 2Y22A3 2Y32A4 2Y4
1G2G
VC
CG
ND
C510
.1UF_0402
1 2
C530
.1UF_0402
1 2
C548
.1UF_0402
1 2
CP4
8P4C_220PF1 82 73 64 5
C549
@.1UF_0402
1 2
U43C74HCT32
9
108
14
7
C550
@.1UF_0402
1 2
U39
74HCT273
24 57 68 9
13 1214 1517 1618 19
3
11
20
1
10
Q0D1 Q1D2 Q2D3 Q3D4 Q4D5 Q5D6 Q6D7 Q7
D0
CLK
VC
C
CLR GN
D
C384 .1UF_04021 2
CP5
8P4C_220PF1 82 73 64 5
U43B74HCT32
4
56
14
7
C531
1UF_25V_0805
1 2
U43D74HCT32
12
1311
14
7
U41
@74HCT244
2 184 166 148 12
11 913 715 517 3
119
2010
1A1 1Y11A2 1Y21A3 1Y31A4 1Y42A1 2Y12A2 2Y22A3 2Y32A4 2Y4
1G2G
VC
CG
ND
C514
.1UF_0402
1 2
CP6
8P4C_220PF1 82 73 64 5
JP14
INT_KB_CONN.
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
25
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324D
umm
y
R353100K_0402
1 2
R342100K_0402
1 2
CP9
8P4C_220PF1 82 73 64 5
CP7
8P4C_220PF1 82 73 64 5
CP88P4C_220PF1 8
2 73 64 5
R328
0_040212
ADB[0..7]<28>
KSO[0..15]<28>
KSI[0..7]<28,30>
BEEP <24>
LID_OUT# <16>PWRBTN_OUT# <16>
SMB_EC_CK1<5,7,15,28,33>SMB_EC_DA1<5,7,15,28,33>
KBA[0..18]<28>
SELIO#<28>
PCM_PME#<21>
AIR_ADP#<33,34>
LID_SW#<27,30>
ENABKL#<15>
THRM#<5>
LAN_PME#<20>VLBA# <16>BATT_LED# <27>
PWR_LED# <27>CHARGE_LED# <27>SWI# <16>
6C/8C#/4C#<33,34>
FDD_PRES#<19>
EC_AGPRST# <15>SOS1# <20>SOS5# <20>
CRT_ON# <15>EC_WAKEUP# <16>
PROCHOT#<5>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
WHEN R=0,Vbe=1.35VWHEN R=33K,Vbe=0.8V
- +Power BTN
Power ON Circuit RTC Battery
W=40mils
USB Over Current
Note:
USB_AS=USB_BS=Trace width=40mils
W=40mils4516
�'()*)'+,*-+0�1)+..*)-+/�
USB Port 0
W=40mils4516
�'()*)'+,*-+0�1)+..*)-+/�
USB Port 1
LID Switch & Function Button
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30 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
RTCPWR
EC_ON
ON/OFFBTN#ON/OFF
OVCUR#0
OVCUR#2
USB0D-USB0D+USBP0+
USBP0-
USB0D-USB0D+
USBP2+ USB2D+USBP2- USB2D-
USB2D-USB2D+
ON/OFFBTN#
+5VALW
+RTCVCC
CHGRTC
+5VALW
+3VALW
+3VALW +3VALW
+3VALW +3VALW
+3V
+3V
+5V USB_BS +3VUSB_AS
USB_AUSB_AS
USB_BS USB_B
+3VALW
+5VS+5VS
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
12
D30
RLZ20A
22K
22K
Q36DTC124EK
2
13
C500
1000PF_0402
12
D33
HSM126S
1
23
C521
.1UF_0402
12
BATT1
RTCBATT
12D27
DAN202U
1
23
R3394.7K_0402
12
R329100K_0402
12
R32222K_0402
1 2
R350
1M_0402
12
R359150K
12
C5061UF_0805_X7R
12
R349 20K_04021 2
R34410K_0402
12
R351 0_04021 2
R35710K_0402
12
U8
TPS2042
12
56
8
34
7GNDIN
OC2#OUT2
OC1#
EN1#EN2#
OUT1
R75100K_0402
12
C159
.1UF_0402
12
C158
.1UF_0402
12
R74 47K_04021 2
R76 47K_04021 2C163
.1UF_0402
12
R72100K_0402
12
L34
FBM-11-451616-800T1 2
+ C162
150UF_10V_E
L13FBM-11-160808-121
1 2
L14FBM-11-160808-121
1 2
C11
.1UF_0402
12
C13
1000PF_0402
12
C12 @150PF_04021 2
C10 @150PF_0402
1 2
L35
FBM-11-451616-800T1 2
C157
1000PF_0402
12
JP3
USB_CONN
1234
VCCD-D+GNDL33
FBM-11-160808-1211 2
L32FBM-11-160808-121
1 2
+ C161
150UF_10V_E
C154
.1UF_0402
12
C155 @150PF_04021 2
C156 @150PF_0402
1 2
U36B
74LVC125
5 6
4
U36A
74LVC125
2 3
1
14
7
G
D
S
Q34
@2N7002
2
13
U38B74LVC14
3 4
714
U38E74LVC14
11 10
714
U38F74LVC14
13 12
714
U38A
74LVC14
1 2
147 R373
10K_0402
12
JP4
USB_CONN
1234
VCCD-D+GND
JP11
SUYIN 12750AR-16G2T-9
1 23 45 67 89 10
1214
111315 16
R396 10K_04021 2
Q43
3904
23
1
R395 10K_0402
1 2
C555
100PF_0402
12
ON/OFF <28>
EC_ON# <36>
RSMRST# <16>
EC_ON<28>
ITP_PWROK <7>VGATE<32>
ICH_VGATE <16>
OVCUR#2 <17>
OVCUR#0 <17>
USBP0+<17>USBP0-<17>
USBP2+<17>USBP2-<17>
VR_ON#<31>
KSO17<28>KSI0 <28,29>KSI1<28,29>KSI2 <28,29>KSI3<28,29>
INT_MIC-<24> INT_MIC+ <24>
SCRLED# <28>CAPSLED#<28> NUMLED# <28>
LID_SW#<27,29>
CK408_PWRGD# <14>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+5VALW to +5V Transfer
+3VALW to +3V Transfer
+5VALW to +5VS Transfer
+3VALW to +3VS Transfer
+1.8VALW to +1.8VS Transfer
1.8VALW/+1.5VS Power direct provide
����������� 0.1
��-����������
31 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
SYSON#
SUSON
SUSONSYSON#
SUSP
SUSP
SUSP
SYSON#
SYSON#
VR_ON
RUNON
SUSP
RUNON
RUNON
VR_ON#
+12VALW
+5V
+12VALW
+5VALW
+3V
+3V
ALW
+5VALW +5VALW
+5VS
+12VALW
+5VALW
+5VALW
+3VALW +3VS
+5VALW
+12VALW
+3VALW+CPU_CORE
+1.8VS+1.8VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
R55
47K_0402
12
G
D
S
Q62N7002
2
13
C355
.01UF_0402
12
U20
SI4800
1234
8765
SSSG
DDDD
U11
SI4800
1234
8765
SSSG
DDDD
C230
22UF_10V_1206
12C234
10UF_6.3V_P
12
C360
.1UF_0402
12
C228
.1UF_0402
12
C361
10UF_10V_1206
12
R175100K_0402
12
R174
1M_04021
2
R164470_0402
12
R121470_0402
12
G
D
SQ212N7002
2
13
G
D
S Q122N7002
2
13
Q25
@SMO5
123
C368
4.7UF_10V_P1
2
+ C36233UF_D2_16V
12
+ C232100UF_D_16V6.3V
12
C554
.1UF_0402
12G
D
SQ422N7002
2
13
R3931M_0402
12
R378100K_0402
12
C552
.01UF_0402
12
G
D
S
Q38
2N7002
2
13
R354470_0402
12
U44 SI48001234
8765
SSSG
DDDD
C553
22UF_10V_1206
12
C515
4.7UF_10V_P
12
G
D
S
Q162N7002
2
13
R132470_0402
12
C240
22UF_10V_1206
12
C237
.1UF_0402
12
C23310UF_6.3V_P
12
+ C551100UF_D_16V
12
+ C235100UF_D_16V
12
G
D
SQ182N7002
2
13
U13 SI48001234
8765
SSSG
DDDD
R352
10K_0402
12
G
D
S
Q372N7002
2
13
G
D
S Q33@2N7002
2
13
G
D
S Q29@2N7002
2
13
R316
@330
12
R340@100K_0402
12
R251470_0402
12
C39510UF_6.3V_P
12
C428
22UF_10V_1206
12
C422
.1UF_0402
12
G
D
S
Q242N7002
2
13
U27 SI48001234
8765
SSSG
DDDD
SYSON<28,33,37>
SUSP#<23,27,28,36,37>
SUSP<23>
VR_ON<28,32>
VR_ON#<30>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VOLTS
CPU-CORE
OUTPUT
A1 CPU Silicon set DSoff =1.2VPR25=13.3K,PR24=39.2KA2 CPU Silicon set DSoff =1.0VPR25=20K,PR24=32.4KFor A1,A2 CPU Silicon stepping PQ37 is pop and PR27=9.31KFor B0 CPU Silicon stepping PQ37 is pop and PR27=37.4K ADY13 LA-1271 0.1
CPU VCORE
32 37Monday, September 10, 2001
Compal Electronics, Ltd.Title
Size Document Number Rev
Date: Sheet of
VTTLX
B+
+5VALWP
B++
+CPU_CORE
B++
B++
+CPU_CORE
+5VALWP
+3VALWP
+3VALWP
+1.8VALWP
+1.2VP
+3VALWP
PC
11
22
00
PF
PL2
HK-AE26A0R6
PD2EC31QS04
21
PC9
4.7UF_1210_25V
PC6
4.7UF_1210_25V
PR6
01 2
PC41
10UF_1206_6.3V
PC151UF_0805
PR42 01 2
PC104.7UF_1210_25V
PC8
4.7UF_1210_25VPC7
4.7UF_1210_25V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PC19
4.7UF_0805_10V
PR28
12.7K_1%
12
PQ3SI4362DY
365 7 8
2
4
1
PQ1
IR7811A
365 7 8
2
4
1
PC23
4.7UF_0805_10V
PQ2IR7811A
365 7 8
2
4
1
PQ4SI4362DY
365 7 8
2
4
1
PR29
30.1K_1%
12
PR27
9.31K_1%
12
PR10
1mR
12
PR1
10K
12
PC290.1UF_0805_25V
PR2
332_1%
12
PR3
475_1%
12PR4
475_1%
12PR5
392_1%
12
PR7 012
PR31
619_1%
12
PR15 012
PR11 012
PR12 012
PR19
1KPC20
330PF
PC
39
0.1
UF
_0
80
5_
25
V
12
PC374.7UF_1210_25V
PC33
4.7UF_1210_25V
PC34
4.7UF_1210_25V
PC35
4.7UF_1210_25V
PC
38
22
00
PF
PC36
4.7UF_1210_25V
PQ7IR7811A
365 7 8
2
4
1
PR39
0
1 2
PQ9SI4362DY
365 7 8
2
4
1
PR36
1mR12
PL3
HK-AE26A0R6
PC16
4.7UF_0805_10V
PQ6
IR7811A
365 7 8
2
4
1
PR40
1
12
PD3EC31QS04
21
PC31
1UF_0805
PR17 10K1 2
PR20
332_1%
12
PR21 475_1%
1 2
PC18
0.1UF_0805_25V
PC2
330PF
PC4
180PF
PC5
180PF
PR8
1012
PL1
KC-FBM-L11-322513-201LMAT
PC
12
0.1
UF
_0
805
_25V
12
PC421UF_0805
PR26
30K
12
PR2310K
12
PR9 012
PR24
32.4K_1%
12
PC22
0.01U_50V
PC30
0.1U_16V
PC3330PF
+PC32
22UF_B_6.3V
PC21
180PF
PC24
0.01U_50V
PR25
20K_1%
PR1611 2
PQ8SI4362DY
365 7 8
24
1
PC1
1000PF
PR1401 2
PQ38
2SA1036K
23
1
PQ37 2N7002
2
13
PQ35
2N70022
13
PQ36
2N7002
21
3
PR30
0
PD1RB051L-40
12
PD4
RB051L-40
12
PU1 SC1474
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 37
38 DRN1
TG1
BST1
VIDFB
VIDB
DPRSL
OSB
HYS
VDPR
VID4
VID3
VID2
VID1
VID0
SS
PWRGD
BST2
TG2
DRN2
V5_2
BG2
PGND2
CORE
DAC
GND
ISH2
CL2
CMP2
CMPRF
VCCA
CLRF
CMP1
CL1
ISH1
EN
PGND1 BG1
V5_1
PR32
@0
+
PC13
220UF_D2_4V_25m
+PC14
220UF_D2_4V_25m
PC25
4.7UF_0805_10V
PC26
330PF
CPU_VID3<6>
CPU_VID4<6>
CPU_VID1<6>
CPU_VID0<6>
PM_DPRSLPVR<6,16>
CPU_VID2<6>
VR_ON<28,31>
PM_STPCPU#16>
VGATE<30>
PM_GMUXSEL <16>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Detector
Precharge detector15.9V/13.2V FORADAPTOR
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Vin Detector17.93V/17.2V
PCN2 battery connector pin assignment
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33 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
PACIN
SYSON
ADPIN
ADPGND
ADPGND
BATT_TEMP
BATT++
ADPIN
BA
TT
+
VIN
+5VALWP
BATT++
+5VP
RTCVREF
B+
+5VALWP
+5VALWP
RTCVREF
VIN VIN
VS
+5VALWP
+5VALWP
BATT+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PC461000PF
12
VIN
GND
AIR_ADP
PCN1RP34-8RD-3PDL2J
3
2
1
4 5 6 7
PC481000PF
12
PC47100PF
12
PC45100PF
12
PD7@BAS40-04
23
1
PD8@BAS40-04
2 3
1
PQ122N7002
2
13
PC50
1000PF
12
PC
510.
1UF
_16V1
2
PC440.1UF_0805_25V
12
PR43100K_0402
12
PR49 10012
PR48100
1 2
PR5410K
12
PR53499K_1%
12
PR55215K_1%
12
PR6047K
12
PR50100K
1 2
PR511M_1%
12
PR52499K_1%
12
PCN2BTC-07GR1 7P
1234567
PR461K
12
PD6
@BAS40-04
23
1
PR47
6.49K_1%
1 2
PR451K
1 2
100K
100K
PQ11DTC115EUA
2
13
100K
100K
PQ13DTC115EUA
2
13
PD9RB751V
12
PD10RB751V
12
1
2
PCN3@2DC-0007B200
1
2
PL5
FBM-L11-453215-900LMAT
1 2
PL6
FBM-L11-453215-900LMAT
1 2
PL7
FBM-L11-453215-900LMAT
1 2
PD
5@
EC
10Q
S04
12
PC540.1UF_16V
12
PZD2RLZ5.1B
12
PC531000PF
12
PC520.01UF
12
PR5784.5K_1%
12
PR6220K_1%
12
PR5810K
12
PR6410K
12
PR5910k
1 2
PR6122K
1 2
PR561M_1%
1 2
PR6310K
12
+
-
PU5BLM393A
5
67
+
-
PU5A
LM393A
3
21
84 PC49
1000PF
12
PR4410_1206
12
PZD1RLZ24B
12
PR161
100K
PR162
1K_1%
PR163
@1K_1% PC430.1UF_0805_25V
12
AIR_ADP# <29,34>
BATT_TEMP <28>
SYSON <28,31,37>
SHDN#<5,35>
SMB_EC_DA1 <5,7,15,28,29>
SMB_EC_CK1<5,7,15,28,29>
ACIN <17,28,35>
PACIN <34>
ACON<34>
PACIN <34>
6C/8C#/4C# <29,34>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
ChargerIadp=0~3.22A
4S LI-IONCharge voltage
IREF=1.746*IchargeIREF=0~5V
OVP voltage :
LI-4S :18.3V----BATT-OVP=4.04V
BATT-OVP=0.2206*BATT++
Iair=0~2.26A<-----Actually about 3A
3S LI-ION : 12.75V
NI-MH : 17.00V
LI-3S :13.5V----BATT-OVP=3.82V
����������� 0.1
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34 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
ACON
LXCHRG
ACOFF#
ACOFF#
BATT+
VIN
VIN
BATT+
B+P2
P3
B+++
BATT++
+5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PC691500PF
1 2
PC652200PF
1 2
PU6MB3878
1
2
3
4
24
23
22
21
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
-INC2
OUTC2
+INE2
-INE2
+INC2
GND
CS
VCC(o)
FB2
VREF
FB1
-INE1
+INE1
OUTC1
OUTD
-INC1
OUT
VH
VCC
RT
-INE3
FB3
CTL
+INC1
PC592200PF
1 2
PC624700PF
1 2
PC640.1UF_16V
12
PC630.1UF_16V
1 2
PQ17FDS4435
365 7 8
2
4
1
PC
704.
7UF
_121
0_25
V1
2
+
PC
6868
UF
_EC
_25V
12
PC
714.
7UF
_121
0_25
V1
2
PC554.7UF_1210_25V
12
PC564.7UF_1210_25V
12
PD11
1SS355
1 2
PC570.1UF_0805_25V
12
PC582200PF
PC600.1UF_0805_25V
1 2
PR791K
1 2
PR8166.5K_1%
1 2
PR85330K
1 2
PR7421K_1%
12
PR83100K_1%
1 2
PR8410K
12
PR7610K
1 2
PR71100K
12
PR8640.2K_1%
12
PR88152K_0.1%
12
PR820.02_2512_1%1 2
PR7510K_1%
12
PR89309K_0.1%
12
PR690
12
PR6747K
1 2
PR7247K_0402
1 2
12
PR7315.8K_1%
12
PR8710K
12
PC660.1UF_0805_25V
1 2
PQ14SI4835DY
365
78
2
4
1
PR66200K_0402
12
PQ15SI4835DY
3 65
78
2
4
1
PR68150K_0402
12
PQ16SI4835DY
3 65
78
2
4
1
100K
100K PQ18DTC115EUA
2
13
PR7747K
1 2
PR78@
12
PC671000PF
12
PR650.02_2010_1%
12
PL8
FBM-L11-322513-151LMAT
1 2
PQ20TP0610T
2
13
G
D
S PQ192N7002
2
13
PR70
10K
12
PC7310PF
1 2
PC7422PF
1 2
PR92
2.2K
12
PR91300K_0.5%
12
PR93143K_0.5%
12
PC750.1UF_16V
12
PC760.01UF
PR90205K_1%
12
PC61.01UF_0402_16V
12
PC72.01UF_0402_16V
12
+
-
PU7ALM358
3
21
84
PD13EA60QC04
1 3
2
PL915UH_SPC-1205PA
1 2
PR164
305K_0.1%PQ402N7002
2
13
PR165
100K
100K
100K
PQ41
DTC115EK2
13
PC154
0.1UF
PACIN<33>
ACON<33>
IREF<28>
FSTCHG <28>
ACOFF <28>
AIR_ADP#<29,33>
BATT-OVP<28>
6C/8C#/4C# <29,33>
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A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+3.3V/+5V/+12V
+3.3V Ipeak = 6.66A ~ 10A
+5V Ipeak = 6.66A ~ 10A
Recovery at 45 degree CCPU thermal protection at 85 degree C
����������� 0.1
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35 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
FLYBACKSNBBST31
DH31
DH51
POK
BST51
CSL5
LX3
DH
3
DL5CSH5
DL3
CSH3
+5VALWP
VS
VL
B++++
B++++
VL
+5VALWP
+12VALWP
B+
+3VALWP
VL
VL
+5VP
NC_TEST1
NC_TEST2
2.5VREF
VL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PC840.1UF_0805_25V
1 2
+
PC
105
150U
F_D
_6.3
V_F
P12
PT1SDT-1205P-100
1
4
3
2
PC
834.
7UF
_121
0_25
V
12
PC97@1000PF
12
PD14EC11FS2
12
PC790.1UF_0805_25V
1 2
PC
894.
7UF
_121
0_25
V
12
+
PC
106
150U
F_D
_6.3
V_F
P12
PC
904.
7UF
_121
0_25
V
12
PC772.2UF_1206_25V
1 2
PC
7847
0PF
_080
5_10
0V
12
PC95@1000PF
12
PC
824.
7UF
_121
0_25
V
12
PQ21SI4800DY
36 578
2
41
PQ23SI4810DY
36 578
2
4
1
PC
800.
1UF
_080
5_25
V
12 P
C81
2200
PF
PC
8722
00P
F
PC
880.
1UF
_080
5_25
V
12
PC
930.
1UF
_080
5_25
V
12
PC
854.
7UF
_120
6_10
V
12
PC
860.
1UF
_16V
12
PC
924.
7UF
_121
0_25
V
12
PR9710_1206
12
PR1030.012_2512_1%
12
PR980_0402
12
PR107@0_0402
1 2
PR9422_1206
12
PR960_0402
12
PR112@100K_0402
12
PD17EP10QY03
21
PQ22SI4800DY
365 7 8
2
4
1
PQ24SI4810DY
365 7 8
2
4
1
PR950_0402
1 2
PR990_0402
1 2
PD18@RB751V
1 2
PR114
10K_0402_1%
12
PR10910.2K_0402_1%
12
PC
91
0.1U
F_0
805_
25V
12
PD15DAP202U
1
2 3
PL10
FBM-L11-322513-151LMAT
12
PR1010.012_2512_1%
12
PL11SLF12565T-100M
12
PR105
3.57K_1%
12
+
PC
99
150U
F_D
_6.3
V_F
P1
2
PR
111
10K
_040
21
2
+
PC
98
150U
F_D
_6.3
V_F
P1
2
PD16EP10QY03
21
PR11847K_1%
PR120100K_1%
PR121100K_1%
PR117
2.15K_1%PR11916.9K_1%
PC
114
1UF
_080
5_25
V
PC111
0.047UF_16V
12
PR11347K_0402
12
PH
110
K_1
%_0
805
[email protected]_04021
2
PR1001M_0402
12
PC94
47PF_0402
12
PC108100PF_0402
12
PC110
@100PF_0402
12
PR1022M_0402
12
PC9647PF_0402
12
PC1131000PF
12
+
-
PU9A
LM393A3
21
84
PR110@0
12
PR115
@0
12
PR106@300K_0402
12
PR10410K_0402
1 2
PC1034.7UF_1206_10V
12
PR1080_0402
1 2
PC102100PF_0402
12
PU8
MAX1632
2624
25
27
123
10
8
451816171920141312159611
23
7
28
2122
LX3DL3
BST3
DH3
CSH3CSL3FB3SKIP#
GN
D
12OUTVDD
BST5DH5LX5DL5
PGNDCSH5CSL5
FB5SEQREF
SYNCRST#
SHDN#
TIME/ON5
RUN/ON3
VL
V+
PC1120.047UF_16V
12
PR116
47K_0402_1%
12
PC104
680PF_0402
12
PR167
@
PR166
@
SHDN# <5,33>
ACIN<17,28,33>
���
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��
��
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+1.8VALW/+1.5VS
+1.8V+-5%
+1.5VS+-5%
����������� 0.1
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36 37Monday, September 10, 2001
�� ���������������������Title
Size Document Number Rev
Date: Sheet of
LX18
2.5VREF
CHGRTCP
+1.5VS
+5VALW+5VALWP
+12VALW
+3VALW
+12VALWP
+3VALWP
+2.5V
+1.8VALW+1.8VALWP
+2.5VP
+1.5VSP
+5VALWP
+1.8VALWP
2.5VREF
VS
+1.5VSP+1.8VALWP
+5VALWP
+5VP
VIN
CHGRTC
RTCVREF
BATT+
B+
VS1
VS
VL
+1.25V+1.25VP
PJP24MM
21
PJP62MM
21
PJP73MM
21
PJP53MM
21
PJP43MM
21
PJP32MM
21
PC1184.7UF_1206_25V
12
PQ272SC2411K
21
3
+ PC116150UF_D_6.3V_KO
12
PC1212200PF
12
+
-
PU9BLM393A
5
67
84
PD19RB751V
12
PQ282SA1036K
23
1
PD
20R
B05
1L-4
0
12
PR1261K
1 2
PL125UH_SPC_06704-5R0A
12
PC1250.01UF
12
S
GD
PQ26SI3445DV
3
6
24 5
1
PR133100K_1%
12
PR13138.3K_1%
12
PR12510K
12
PC12468PF
S
GD
PQ25SI3442DV
3
6
245
1
PC
119
0.1U
F_1
6V
12 PC
120
220P
F
+ PC115150UF_D_6.3V_KO
12
PC
123
0.01
UF
100K
100K
PQ29DTC115EK
2
13
PC
117
4.7U
F_1
206_
25V
+
-
PU7BLM358
5
67
PR
124
0
12
PR
123
5.1K
12
PR128
200K_1%12
PR
129
300K
_0.5
%
12
PR132
5.1K1 2
PR
130
100K
12
PD21
RLS4148
12
PD23RLS4148
12
PZD3RLZ4.3B
12
PR139200_0805
12
PR144200
1 2
PR1361.5K_1206
12
PR1371.5K_1206
12
PR1381.5K_1206
12
PR141100K
12
PR14322K
1 2
PC
126
0.22
UF
_120
6_25
V
12
PZD5RLZ16B
12
PR135200_1206
1 2
PQ31TP0610T
2
13
PD22RLS4148
12
PZD4RLZ5.1B
12
PC1294.7UF_1206_25V
12
PU10S-81233SG
2
1
3IN
GND
OUT
PR14010K
1 2
PC1270.1UF_0805_25V
12
PR142150K
12
PC1301UF_0805_25V
12
PC1280.1UF_16V
12
PR134200_1206
1 2
100K
100K
PQ30DTC115EK
2
13
PC
122
0.1U
F_1
6V12
PJP83MM
21
PR1271M
12
PR122
10K
12
PC
147
0.1U
F_1
6V12 PC148
470PF
12
PR34200
1 2
PR331.5K_1206
12
SUSP# <23,27,28,31,37>
EC_ON#<30>
2.5VREF <35>
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A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
INC.
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,B
(+2.5V : I_peak =8.5A)
+1.25V
�������
ADY13 LA-1271 0.1
DDR POWER 2.5V & 1.25V
COMPAL ELECTRONICS, INC
37 37Monday, September 10, 2001
Title
Size Document Number Rev
Date: Sheet of
2.5DL
2.5VLX
2.5_B+
FB
2.5DH
B+
+5VALW
+2.5VP
+1.25VP
+2.5VP
+2.5VP
NC_TEST3
NC_TEST4
VS
+2.5VP
SDREF
PC1310.1UF_0805_25V
PC1334.7UF_1210_25V
PC1324.7UF_1210_25V
PC1380.1UF_16V
PC136
0.1UF_0805_25V
PR15115K
1 2
PR15384.5K
12
PC1354.7UF_1206_16V PL14
4.7UH_SPC-1205P-100
PD241SS355
21
PC139@150PF_50V
PR1450_080512
PR149 0
PR147 10PC1344.7UF_1206_16V
PC140@1UF_0805_16V
+
PC137150UF_D_6.3V
PC144
4.7UF_1206_16V
12
PC1451000PF
12
PL155UH_SPC_06704-5R0A
12
+
PC142220UF_D_4V_FP
12
PC1460.1UF_16V
12
PU12
CM8500
11
12
6
16
13
8
7
5
15
3 14
4
2
1
10
9
VFB
AGND2
SD
VCC2
PGND2
AGSEN
VIN/2
AGND1
PVDD2
VL1 VL2
PGND1
PVDD1
VCC1
VCCQ
AGND
PR1551K
12
PR156100K
12
PC143
1000PF
1 2
PQ33
SI4810
1 3 4
8 7 6 5
2S S G
D D D D
S
PQ32
SI4800DY
134
8765
2
SSG
DDDD
S
PU11
MAX1714A
14
19
20
13
1
12
11
9
5
48
2
7
16
18
6
3
10
17
15 VDD
BST
LX
DL
DH
PGND
N/C
N/C
OUT
FBAGND
N/C
REF
TON
SKIP
ILIM
SHDN
PGOOD
V+
VCC
PR15210K_1%
PR15015K_1%
PR148 0
PL16
FBM-L11-322513-151LMAT
1 2
PR35
0
PR37
@0
PR38
@0
+PC149
47UF_D_6.3V
+PC150
@220UF_D_4V_FP
12
PR157
100K
12
PQ39
2N7002
2
13
PR158
@10K
12
PC
151
0.1
UF
_1
6V
12
PR160100K_0.5%
12
PC1520.01UF
PR159100K_0.5%
12
12
+
-
PU13BLM358
5
67
84
PD26
@EP10QY03
21
PD25
@EP10QY03
21
+
-
PU13ALM358
3
21
84
PR15410
12
PC141
0.1UF_16V
12
SYSON<28,31,33>
SUSP#,36>
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