Upload File

10-verilog timing and delays

41
Digital System Design Verilog ® HDL Timing and Delays Maziar Goudarzi

Upload: geetika-arora

Post on 02-Dec-2014

178 views

Category:

Documents


2 download

Report

TRANSCRIPT

Page 1: 10-Verilog Timing and Delays

Digital System Design

Verilog® HDLTiming and Delays

Maziar Goudarzi

Page 2: 10-Verilog Timing and Delays

2005 Verilog HDL 2

Today Program

Delays and their definition and use in Verilog

Page 3: 10-Verilog Timing and Delays

2005 Verilog HDL 3

Introduction:Delays and Delay Back-annotation

Page 4: 10-Verilog Timing and Delays

2005 Verilog HDL 4

Introduction (cont’d)

Functional simulation vs. Timing simulation Delays are crucial in REAL simulations

Post-synthesis simulation Post-layout simulation

FPGA counter-part: Post-P&R simulation

Delay Models Represent different physical concepts Two most-famous models

Inertial delay Transport delay (path delay)

Page 5: 10-Verilog Timing and Delays

2005 Verilog HDL 5

Delay Models:Inertial DelayThe inertia of a circuit node to change

valueAbstractly models the RC circuit seen at

the nodeDifferent types

Input inertial delay Output inertial delay

Page 6: 10-Verilog Timing and Delays

2005 Verilog HDL 6

Delay Models:Transport Delay (Path Delay)Represents the propagation time of

signals from module inputs to its outputsModels the internal propagation delays of

electrical elements

Page 7: 10-Verilog Timing and Delays

Specifying Delays inVerilog

Delays in Verilog

Page 8: 10-Verilog Timing and Delays

2005 Verilog HDL 8

Specifying Delays in Verilog

Delays are shown by # sign in all Verilog modeling levels

Supported delay types Rise, Fall, Turnoff types Min, Typ, Max values

Page 9: 10-Verilog Timing and Delays

2005 Verilog HDL 9

Delay Types in Verilog

Rise Delay From any value to 1

Fall Delay From any value to 0

Turn-Off Delay From any value to z

From any value to x Minimum of the three delays

Min/Typ/Max Delay values

Page 10: 10-Verilog Timing and Delays

2005 Verilog HDL 10

Specifying Delays in Verilog (cont’d)

Rise/Fall/Turnoff delay types (cont’d) If no delay specified

Default value is zero If only one value specified

It is used for all three delays If two values specified

They refer respectively to rise and fall delays Turn-off delay is the minimum of the two

Page 11: 10-Verilog Timing and Delays

2005 Verilog HDL 11

Specifying Delays in Verilog (cont’d)

Min/Typ/Max Values Another level of delay control in Verilog Each of rise/fall/turnoff delays can have min/typ/max valuesnot #(min:typ:max, min:typ:max, min:typ:max) n(out,in)

Only one of Min/Typ/Max values can be used in the entire simulation run

It is specified at start of simulation, and depends on the simulator used

ModelSim optionsModelSim> vsim +mindelays ModelSim> vsim +typdelaysModelSim> vsim +maxdelays

Typ delay is the default

Page 12: 10-Verilog Timing and Delays

2005 Verilog HDL 12

Specifying Delays in Verilog (cont’d)

General syntax#(rise_val, fall_val, turnoff_val)

#(min:typ:max, min:typ:max, min:typ:max)

Gate-Level and Dataflow Modeling All of the above syntaxes are valid

Behavioral Modeling Rise/fall/turnoff delays are not supported Only min:typ:max values can be specified

Applies to all changes of values

Page 13: 10-Verilog Timing and Delays

Delays inGate-Level Modeling

Delays in Verilog

Page 14: 10-Verilog Timing and Delays

2005 Verilog HDL 14

Delays in Gate-Level Modeling

The specified delays are output-inertial delaysand #(rise_val, fall_val, turnoff_val) a(out,in1, in2)

not #(min:typ:max, min:typ:max, min:typ:max) b(out,in)

Examples:and #(5) a1(out, i1, i2);

and #(4, 6) a2(out, i1, i2);

and #(3, 4, 5) a2(out, i1, i2);

and #(1:2:3, 4:5:6, 5:6:7) a2(out, i1, i2);

Page 15: 10-Verilog Timing and Delays

2005 Verilog HDL 15

Delays in Gate-Level Modeling (cont’d)

Page 16: 10-Verilog Timing and Delays

2005 Verilog HDL 16

Delays in Gate-Level Modeling (cont’d)

Page 17: 10-Verilog Timing and Delays

Delays inDataflow Modeling

Delays in Verilog

Page 18: 10-Verilog Timing and Delays

2005 Verilog HDL 18

Delays in Dataflow Modeling

As in Gate-Level Modeling the delay is output-inertial delay

Regular assignment delay syntaxassign #delay out = in1 & in2;

Implicit continuous assignment delaywire #delay out = in1 & in2;

Net declaration delay Can also be used in Gate-Level modelingwire #delay w;

Page 19: 10-Verilog Timing and Delays

2005 Verilog HDL 19

Delays in Dataflow Modeling (cont’d)

Exampleswire #10 out = in1 & in2; wire out;

assign #10 out = in1 & in2;

wire #10 out;

assign out = in1 & in2;Note: pulses with a width less than the delay are not propagated to output

Page 20: 10-Verilog Timing and Delays

2005 Verilog HDL 20

Delays in Dataflow Modeling (cont’d)

// Lumped delays in dataflow modelingmodule M(out, a, b, c, d);output out;input a, b, c, d;

wire e, f;

// Lumped delay modelassign e=a & b;assign f=c & d;assign #11 out = e & f;

endmodule

Page 21: 10-Verilog Timing and Delays

Delays inBehavioral Modeling

Delays in Verilog

Page 22: 10-Verilog Timing and Delays

2005 Verilog HDL 22

Delay in Behavioral Modeling

Only min:typ:max values can be set i.e. rise/fall/turnoff delays are not supported

Three categories Regular delays Intra-assignment delays Zero delay

Page 23: 10-Verilog Timing and Delays

Path (Transport ) Delays in Verilog

Delays in Verilog

Page 24: 10-Verilog Timing and Delays

2005 Verilog HDL 24

Transport Delays in Verilog

Also called Pin-to-Pin delay Path delay

Gate-level, dataflow, and behavioral delays Property of the elements in the module (white box)

Styles: Distributed or Lumped

Path delay A property of the module (black box) Delay from any input to any output port

Page 25: 10-Verilog Timing and Delays

2005 Verilog HDL 25

Transport Delays in Verilog (cont’d)

Page 26: 10-Verilog Timing and Delays

2005 Verilog HDL 26

Transport Delays in Verilog (cont’d)

specify block Assign pin-to-pin delays Define specparam constants Setup timing checks in the design

Page 27: 10-Verilog Timing and Delays

2005 Verilog HDL 27

specify blocks

Parallel connection Syntax:

specify (<src_field> => <dest_field>) = <delay>;endspecify

<src_field> and <dest_field> are vectors of equal length

Unequal lengths, compile-time error

Page 28: 10-Verilog Timing and Delays

2005 Verilog HDL 28

specify blocks (cont’d)

Full connection Syntax:

specify (<src_field> *> <dest_field>) = <delay>;endspecify

No need to equal lengths in <src_field> and <dest_field>

Page 29: 10-Verilog Timing and Delays

2005 Verilog HDL 29

specify blocks (cont’d)

Page 30: 10-Verilog Timing and Delays

2005 Verilog HDL 30

specify blocks (cont’d)

specparam constants Similar to parameter, but only inside specify block Recommended to be used instead of hard-coded delay

numbers

Page 31: 10-Verilog Timing and Delays

2005 Verilog HDL 31

specify blocks(cont’d)

Conditional path delays Delay depends on

signal values Also called State-

Dependent Path Delay (SDPD)

Page 32: 10-Verilog Timing and Delays

2005 Verilog HDL 32

specify blocks (cont’d)Rise, Fall, and Turn-off delays

Page 33: 10-Verilog Timing and Delays

2005 Verilog HDL 33

specify blocks (cont’d)Rise, Fall, and Turn-off delays

Page 34: 10-Verilog Timing and Delays

2005 Verilog HDL 34

specify blocks (cont’d)Min, Typ, Max delays

Any delay value can also be specified as (min:typ:max)

Page 35: 10-Verilog Timing and Delays

2005 Verilog HDL 35

specify blocks (cont’d)

Handling x transitions Pessimistic approach

Transition to x: minimum possible time Transition from x: maximum possible time

Page 36: 10-Verilog Timing and Delays

2005 Verilog HDL 36

specify blocks (cont’d)

Timing Checks A number of system tasks defined for this $setup: checks setup-time of a signal before

an event $hold: checks hold-time of a signal after an

event $width: checks width of pulses

Page 37: 10-Verilog Timing and Delays

2005 Verilog HDL 37

specify blocks (cont’d)Timing Checks

$setup check Syntax:

$setup(data_event, reference_event, limit);

Page 38: 10-Verilog Timing and Delays

2005 Verilog HDL 38

specify blocks (cont’d)Timing Checks

$hold check Syntax:

$hold(reference_event, data_event, limit);

Page 39: 10-Verilog Timing and Delays

2005 Verilog HDL 39

specify blocks (cont’d)Timing Checks

$width check Syntax:

$width(reference_event, limit);

Page 40: 10-Verilog Timing and Delays

2005 Verilog HDL 40

Today Summary

Delays Models

Inertial (distributed and lumped delay) Transport (path/pin-to-pin delay)

Types Rise/Fall/Turn-off Min/Typ/Max Values

Delays in Verilog Syntax and other common features Gate-Level and Dataflow Modeling Behavioral Modeling

Page 41: 10-Verilog Timing and Delays

2005 Verilog HDL 41

Other Notes

Homework 9 Chapter 10:

All exercises Due date: Sunday, Day 11th


VERILOG 설계언어 중급 2일차 - Hanyangmslab.hanyang.ac.kr/IDEC_VERILOG_day2.pdf · 2003. 5. 21. · VERILOG 설계언어 ... Timing Closure 15:40 ~ 17:00 ASIC 개발 실습

Verilog Timing

Verilog Hardware Description Language (Verilog HDL)

Formal Timing Analysis of Digital Circuitssave.seecs.nust.edu.pk/Downloads/quain_thesis.pdf · Timing analysis usually involves determining the timing delays associated with each

A Verilog Primer - inst.eecs.berkeley.eduinst.eecs.berkeley.edu/~eecs151/fa19/files/verilog/Verilog_Primer_Slides.pdf · Verilog Modules I Modules are the building blocks of Verilog

Analog Verilog,Verilog-A Tutorial

Verilog – Sequential Logic - Worcester Polytechnic Instituteusers.wpi.edu/~rjduck/Verilog for synthesis - sequential logic rev... · Verilog – Sequential Logic Verilog for Synthesis

CMPE 415 Verilog Events Timing and Testbenches · Department of Computer Science and Electrical Engineering Verilog Events Timing and Testbenches Prof. Ryan Robucci CMPE 415

Exhaustively Verify SEU Mitigation Techniques …...CDC Reconvergence Synchronizers can only resolve unpredictable values — Synchronizers cannot resolve unpredictable delays Timing

Tutorial Quartusii Timing Simulation Verilog

Implementation of Image Compression Algorithm using Verilog with Area, Power and Timing

Verilog II CPSC 321 Andreas Klappenecker Today’s Menu Verilog, Verilog

Verilog Fundamentals · 2016. 8. 30. · verilog fundamentals hdls history how fpga & verilog are related coding in verilog

Machine Learning Applications in Physical Design: Recent ... · time, delay due to SI •Accurate SI-aware path delays, slacks Timing Reports in SI Mode Timing Reports in Non-SI Mode

Verilog Fundamentals · Verilog Fundamentals. VERILOG FUNDAMENTALS ... Verilog is a HARDWARE DESCRIPTION LANGUAGE. ... Level 2 : Design a digital system using Verilog . (weightage

Verilog HDL 18EC56 Verilog HDL [As per Choice Based Credit ... · The logic synthesis tool will optimize the circuit in area and timing for the new technology. • By describing designs

DESIGNING MULTI-FPGA PROTOTYPES THAT ACT LIKE ASICS · 2015. 10. 29. · synthesis considers only logic cell delays and simple timing models of interconnect delays, physical synthesis

Tut Timing Verilog

Filamentous morphology of bacteria delays the timing of

Digital Design II Spring 2008 Lecture 20: Timing Analysis ... · Static Timing Analysis STA looks for the worst of the following delays in a chip Delay from input to register Delay

Class 14: Timing and Delays - University of Kentucky ...web.engr.uky.edu/~elias/lectures/ln_14.pdfClass 14: Timing and Delays Gate Capacitance (Martin p.261) Modeling of a gate capacitor

Statistical Timing Analysis Under Spatial Correlations...delays, the task of statistical STA is to find the PDF of the circuit delay. The static timing analysis works with the usual

Digital System Design Verilog ® HDL Timing and Delays Maziar Goudarzi

More Verilog - courses.cs.washington.edu · Verilog - 4 Shift Register Example // 8-bit register ... Delays are useful for modeling time ... // Structural Verilog connects test-fixture

Intel Quartus Prime Timing Analyzer Cookbook · Input and Output Delays with Virtual Clocks All input and output delays should reference a virtual clock. With that virtual clock,

Verilog Nonblocking Assignments With Delays, Myths & Mysteries€¦ · It is illegal to use a nonblocking assignment in a continuous assignment statement or in a net declaration

Understanding FPGA Tradeoffs for Software Radio Applications · & Verilog Advanced simulation tools for modeling speed, propagation delays, skew and board layout Faster compilers

ECE 551 Digital Design And Synthesis Lecture 2 Structural Verilog Wrap-Up Timing Controls for Simulation Testbenches Introduction to RTL Verilog

World Class Verilog & SystemVerilog Training · World Class Verilog & SystemVerilog Training SystemVerilog Event Regions, ... an unexpected dependence on the relative timing or ordering

Verilog Nonblocking Assignments with Delays - Myths ...twins.ee.nctu.edu.tw/courses/ip_core_04/resource... · Delay Line Model Sunburst Design Transport Delays ` timescale 1ns / 1ns

VHDL,Verilog and Advanced Verilog

VERILOG - RWTH Aachen Universityhpac.cs.umu.se/teaching/sem-hpsc-14/presentations/Verilog slides.pdf · What is Verilog ? Verilog is a hardware description language(HDL) Verilog is

Introduction to Verilog (Behavioral Modeling). Agenda Gate Delays and User-Defined Primitives Behavioral Modeling Design Examples Hands-on Practice

Synthesis and Timing (Verilog)users.wpi.edu/~rjduck/Synthesis and Timing module 11 rev a.pdf · Jim Duckworth, WPI 1 Synthesis and Timing - Module 11 Synthesis and Timing (Verilog)

Verilog timing scheduling