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Last Class: Introduction

Operating system =interface between user & architecture

Importance of OS OS history:

Change is only constant

User-level Applications

Operating System

Hardware

virtual machine interface

physical machine interface

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Today:OS & Computer Architecture

Modern OS Functionality (brief review)

Architecture Basics Hardware Support for OS

Features

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Modern OS Functionality

CPU management Concurrency (multiple simultaneous

activities) How to achieve it? How to

schedule? How to avoid conflict? Memory management Disk management I/O Device Management Advanced: support for

distributed systems & networks

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Operating Systems = Governments

Infinite RAM, CPU Protect users from each other:

safety Fair allocation of resources To each according to his needs Manage resources efficiently

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Canonical System Hardware CPU: Processor to

perform actual computations

I/O devices: terminal, disks, video, printer…

Memory: data & programs

System Bus: Communication channel between above

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Services & Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

System Calls Trap Instructions

I/O Interrupts, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Protection

OS protects users from each other Users cannot read or write other

user’s memory Protects self from users

Safe from errant or malicious users Code & data protected

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Kernel Mode:Privileged Instructions CPU provides “kernel” mode restricted to

OS Inaccessible to ordinary users Kernel = core of operating system

Privileged instructions & registers: Direct access to I/O Modify page table pointers, TLB Enable & disable interrupts Halt the machine, etc.

Indicated by status bit in protected CPU register

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Protecting Memory:Base and Limit Registers

Hardware support to protect memory regions Loaded by OS before

starting program CPU checks each

reference Instruction & data

addresses Ensures reference in

range

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Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

Traps Trap Instructions

I/O Interrupts, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Interrupts

Interrupt: Let CPU work while doing I/O

I/O is s..l..o..w for CPU I/O device has own processor When finished, device sends interrupt on bus CPU “handles” interrupt

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CPU Interrupt Handling

Handling interrupts: relatively expensive CPU must:

Save hardware state (why?) Registers, program counter

Disable interrupts (why?) Invoke via in-memory interrupt vector (like

trap vector, soon) Enable interrupts Restore hardware state Continue execution of interrupted process

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Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

Traps Trap Instructions

I/O Interrupt vectors, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Traps Special conditions detected by architecture

E.g.: page fault, write to read-only page, overflow, system call

On detecting trap, hardware must: Save process state (PC, stack, etc.) Transfer control to trap handler (in OS)

CPU indexes trap vector by trap number Jumps to address

Restore process state and resume

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Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

Traps Trap Instructions

I/O Interrupt vectors, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Memory-Mapped I/O

Direct access to I/O controller through memory

Reserve area of memory for communication with device (“DMA”) Video RAM:

CPU writes frame buffer Video card displays it

Fast and convenient

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Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

System Calls Trap Instructions

I/O Interrupt vectors, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Synchronization

How can OS synchronize concurrent processes? E.g., multiple threads, processes &

interrupts, DMA CPU must provide mechanism for

atomicity Series of instructions that execute

as one or not at all

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Synchronization: How-To

One approach: Disable interrupts Perform action Enable interrupts

Advantages: Requires no hardware support Conceptually simple

Disadvantages: Could cause starvation

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Synchronization: How-To, II

Modern approach: atomic instructions Small set of instructions that cannot be

interrupted Examples:

Test-and-set (“TST”)if word contains given value, set to new value

Compare-and-swap (“CAS”)if word equals value, swap old value with new

Intel: LOCK prefix (XCHG, ADD, DEC, etc.) Used to implement locks

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Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

System Calls Trap Instructions

I/O Interrupt vectors, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Virtual Memory

Provides illusion of complete access to RAM All addresses translated from physical

addresses into virtual addresses OS loads pages from disk as needed

Keeps track of which pages are in memory (“in core”) and which are on disk

Many benefits, including: Allows users to run programs without

loading entire program into RAM May not fit in entirety (think MS Office)

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Translation Lookaside Buffer

First virtual memory systems performed address translation in software On every memory access! (s..l..o..w..)

Modern CPUs contain hardware to do this: the TLB Hash-based scheme Maps virtual addresses to physical

addresses Fast, fully-associative cache

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Hardware Support

OS Service Hardware Support

Protection Kernel/User ModeProtected InstructionsBase & Limit Registers

Interrupts Interrupt Vectors

System Calls Trap Instructions

I/O Interrupt vectors, Memory-Mapping

Synchronization

Atomic Instructions

Virtual Memory

Translation Lookaside Buffers

Scheduling Timer

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Scheduling & Timers

OS needs timers for: Time of day CPU scheduling

Fairness: limited quantum (e.g., 100ms) for each task

When quantum expires, switch processes

Uses interrupt vector

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Summary

OS relies on hardware for many services Protection Interrupts Traps Synchronization Virtual memory Timers

Otherwise impossible or impractically slow in software

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From Architecture to OS to User

Architectural resources, OS services, user abstractions