04 silica xilinx

Xilinx Confidential

XILINX Aerospace solutionsOlivier MEHAIGNERIE / SILICA Olivier MEHAIGNERIE / SILICA Joel LE MAUFF / XILINXJoel LE MAUFF / XILINXDecember 2008

Xilinx Confidential2008-12-02_Xilinx-CNES CCT FPGA-JLM 2

OUTLINEOUTLINE Xilinx introductionXilinx introduction Products overview Aerospace & Defense introduction Avionics solutions

Products offering Atmospheric Environement Testing & Results RTCA DO-254 / EUROCAE ED-80

Space solutions Product offering Space Environment Testing & Results Mitigations techniques XTMR architecture & TMRtool

Summary


Worldwide leader in programmable solutions Founded in 1984 $1.8B in revenues in FY 08 ~3,500 employees worldwide 20,000+ customers worldwide

Pioneer of the fabless semiconductor model Inventor of the FPGA

First to 180nm, 150nm, 130nm, 90nm and 65nm Currently ship over 98% of high-end 65nm production FPGAs in the world

50% PLD market segment share Larger than all competitors combined

Xilinx FactsXilinx Facts


Innovation at XilinxInnovation at Xilinx

Xilinx Patent HallXilinx Patent Hall

Industrys first 65-nm FPGAs with 30% higher performance * 35% lower dynamic power *

65-nm ExpressFabric technology 2nd Generation Triple-oxide technology Embedded PCIe and GbE interfaces Enhanced Sparse Chevron packaging Columnar architecture (ASMBL) ChipSync IP immersion Differential clock tree Optional FIFO logic XtremeDSP slice Tri-Mode hard Ethernet MAC

1,325 Patents

* Compared to 90nm Virtex-4 FPGAs


Digital Convergence Drives DemandDigital Convergence Drives Demand

In-The-Hand ( CoolRunnerCoolRunner II II ) Cost and size are premium Power is key Shortest time-in-market

The Core Infrastructure ( VirtexVirtex ) Performance & capability

are premium Power & cost constrained Longer time-in-market

Voice

Data

VideoThe Expanding Edge ( Spartan Spartan ) Cost and flexibility are key Moderate Performance Shorter time-in-market


Xilinx Serves Xilinx Serves a Wide Range of Marketsa Wide Range of Markets

Infrastructure WirelessCommunications

Infotainment InstrumentationAutomotive

Crypto Space

Aerospace Aerospace and Defenseand Defense

Displays HandheldsConsumer

Surveillance Test and Measurement

Industrial Scientific and Medical

MilComm Avionics


OUTLINEOUTLINE Xilinx introduction Products overviewProducts overview Aerospace & Defense introduction Avionics solutions



Summary


ISE FoundationSimulation

Timing Analysis

LogicLogic

Simulation

Utilization

Power Analysis

DSPDSPSystem Generator

IP

HW in the Loop

System Design

Programmable MethodologyProgrammable MethodologyAbstracting Away the HardwareAbstracting Away the Hardware

Platform StudioProcessorProcessor

ChipScope Pro


ISEISE Design Suite 10.1Design Suite 10.11 Environment for Logic, Embedded and DSP Design1 Environment for Logic, Embedded and DSP Design

ISEFoundation PlanAhead

ChipScopePro

EDK / Xilinx Platform Studio

System Generator AccelDSP

Efficient logic implementation

Design analysis & planning

Interactive system

debugging

Flexible embedded

system design & programming

DSP system design

(Simulink)

DSP algorithm development

(MATLAB)

Electronic fulfillment for fast access to updates to updates and evaluation


Intellectual Property CoresIntellectual Property CoresAugment Your Own R&D to Augment Your Own R&D to

Maximize Productivity and Reduce riskMaximize Productivity and Reduce riskProgrammable hard IP Immersed in FPGA fabric Advantage over soft IP

2x performance 10x lower power 10x less area

Customizable soft IP Built on FPGA fabric Examples

LogiCORE (from Xilinx) AllianceCORE (from partners) Reference Designs

Advantage over hard IP Most flexible

Library of >400 blocks

IP Hard SoftBasic BlockRAM/FIFO,

System MonitorBaseBlox, Memory I/Fs

Connectivity PHY (ser./par.), PCIe, GE, timing critical I/O logic & clocking

Serial and parallel I/F protocols

Processing PowerPC 440, Crossbar switch, DMA, MCI, Bus I/F

MicroBlaze, peripherals, accelerators

DSP XtremeDSP slice (MAC)

Algorithms, FEC

System functions

Traffic Manager

Example IP for Virtex-5 Platform FPGAs


Density

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Products SolutionsProducts Solutions

HighHigh--End End FPGAsFPGAs

CPLDsCPLDsLow Power

SRAM-basedFeature RichHigh Performance

HighHigh--Volume Volume FPGAsFPGAs

SRAM-basedFeature RichLow Cost

512MC 75KLC 330LC

High Reliability ProductsHigh Reliability Products

XC C&I- grad

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XA

XC C&I-grad

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XA

XC C&I-grad

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XQ from I t

o B-grades

XQR from

M to V-grad

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3 Product 3 Product FamiliesFamilies: : CPLDsCPLDs + + SpartanSpartan + + VirtexVirtex 3 3 CategoriesCategories: XC, XA, XQ(R) : XC, XA, XQ(R)


OUTLINEOUTLINE Xilinx introduction Products overview Aerospace & Defense introductionAerospace & Defense introduction Avionics solutions



Summary


1985 1990 1995 2000 2005 2010

Xilinx Continuous CommitmentXilinx Continuous Commitment

Source: Company reportsXilinx founded: 1984First field programmable gate array (FPGA): 1985

First device qualified to MIL-STD-883: 1989

Rad-tolerant Virtex devices : 2000SEE Consortium formed: 2002

Xilinx on Mars: 2004Xilinx Single-chip Crypto: 2006

Virtex-4 QPro FPGAs: 2007

First Rad-Tolerant devices: 1998

Virtex-4QV FPGAs: 2008

Virtex-II QPro FPGAs: 2004


Xilinx in Aerospace & DefenseXilinx in Aerospace & Defense

A&D drives cutting edge technology Point of Xilinx Technology Spear

2nd Largest vertical segment within Xilinx >$240M segment for Xilinx overall Fastest growing segment within Xilinx Major area of investment and focus

leveraging existing commercial technologyXilinx is the market leader in A & D with over 50% market share


Networked, space-based, precision-guided, rapidly deployable, joint service, modular, and secure.

FPGAs are the perfect fit! Flexible and Reconfigurable Solve new complex Signal Processing

demands System On Chip Capabilities

(Feeds SWAP-C *) Time to Market Security of HARDWARE vs Software

Growth Focusedon Transformation

(*) SWAP-C stands for Size, Weight, Power and Cost


Xilinx Aerospace & Defense Xilinx Aerospace & Defense Integration SolutionsIntegration Solutions

Reduce system complexity and size with integrated features PowerPC processor cores Ethernet MAC PCIe endpoint blocks DSP acceleration engines Digital Clock Management

Increase reliability Less PCB connections / complexity

SWAP-C: Reduced size, weight, power and cost


OUTLINEOUTLINE Xilinx introduction Products overview Aerospace & Defense introduction Avionics solutionsAvionics solutions

Products offeringProducts offering Atmospheric Atmospheric EnvironementEnvironement Testing & ResultsTesting & Results RTCA DORTCA DO--254 / EUROCAE ED254 / EUROCAE ED--8080


Summary


SpartanSpartan--3 family3 familyOptimized Platforms Save CostOptimized Platforms Save Cost

I/Os

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Spartan-3E Platform Logic Optimized

Spartan-3E Platform Logic Optimized

Hibernate modeSuspend modeDevice DNANon-Volatile versionEtc

Spartan-3 Platform For Highest Density & Pin-count Appls

Spartan-3 Platform For Highest Density & Pin-count Appls

Spartan-3A & Spartan-3AN Platform

I/O Optimized

Spartan-3A & Spartan-3AN Platform

I/O Optimized

Spartan-3A DSP Platform DSP Optimized

Spartan-3A DSP Platform DSP Optimized


VirtexVirtex--5 FPGA Family5 FPGA FamilyThe Ultimate System Integration PlatformThe Ultimate System Integration Platform

LogicOn- chip RAM

DSP Capabilities

Serial I/OsParallel I/Os

Logic Logic + Serial DSP + Serial Emb. + Serial

YES YES Samples NowYES

LX LXT SXT FXT

In Production

EasyPath low-risk, conversion-free cost reduction for all platforms: 30-75% cost savings

PowerPC

High-performance logic

High-perf. logic w/ low-power serial I/Os

DSP and memory-intensive apps w/ low-

power serial I/Os

Processing and memory-intensive apps w/

highest-speed serial I/Os

65-nm platforms


Xilinx FPGA roadmapXilinx FPGA roadmap

MontMontBlancBlanc

St. Andrews

TXTTXT

Spartan-3

Greater Logic capacity Flexible On-Chip Memory Greater performance and more I/O standards Broad spectrum of Serdes solutions Abundand DSP resources Reducing Power Through Advanced Design and Process St. Andrews: The Lowest Cost, Easy to Use FPGA Mont Blanc: Highest Performance, Most Advanced FPGA





Summary


Terrestrial SEE testing Terrestrial SEE testing methodologymethodology

11-- QcritQcrit simulationsimulation- when process ground rules available

22-- AcceleratedAccelerated SEE SEE testingtesting @ LANSCE@ LANSCE- when 1st silicon out of fab

33-- AtmosphericAtmospheric testingtesting / Rosetta / Rosetta PlatformsPlatforms- when large quantity of packaged silicon available

a) a) LowLow Noise Underground Noise Underground testingtesting for for ReferenceReference 00 b) Altitude b) Altitude testingtesting ((higherhigher isis betterbetter))


SRAM Cell SEU SimulationsSRAM Cell SEU SimulationsThis activity is still running

Under Xilinx IM2NP ONERA collaboration

Goal:Goal:Better understanding at

component level (CMC, BRAM) of physical phenomena inducedby SEU / MBUs,

SER prediction


AcceleratedAccelerated SEE SEE testingtestingLos Los AlamosAlamos Neutron Science Neutron Science CEnterCEnter

Goal:Goal:Get access to Cross SectionsTesting done on

Virtex (220nm)Virtex-E (180nm)Virtex-II (150nm)Virtex-IIpro (130nm)XPLA3 (350nm) (*)CoolRunner-II (180nm)Virtex-4 (90nm)Spartan-3 (90nm)Spartan-3E/3A (90nm)Virtex-5 (65nm)

Virtex-II became Calibration component


Low Noise Underground TestingLow Noise Underground TestingOCAOCA--LSBB LSBB Reference levelReference level

200 200 VirtexVirtex--IIproIIpro 130nm130nm2 CMC & 0 BRAM upsets3,060,000 3,060,000 devicesdevices hourshoursCMC: 54 FIT/Mb, from 7 to 197FIT/Mb@ 95% confidence intervalBRAM: 86 FIT/Mb, from 0 to 316FIT/Mb@ 95% confidence interval

100 100 VirtexVirtex--5 / 65nm5 / 65nm

LSBB scientific and technical characteristics insure that no Soft Error can occur coming from other sources

e.g. noise.

2 CMC & 1 BRAM upsets663,000 663,000 devicesdevices hourshoursCMC: 138 FIT/Mb, from 17 to 498FIT/Mb@ 95% confidence intervalBRAM: 291 FIT/Mb, from 7 to 1621FIT/Mb@ 95% confidence interval

(No sensitivity from thermal neutrons have been revealed because XILINX devices don't use Bore 10 or BPSG)


Altitude testingAltitude testingOMP + CMB sitesOMP + CMB sites

300 300 VirtexVirtex--5 / 65nm5 / 65nm2884m and 3794m altitude39 CMC & 46 BRAM upsets13,800,000 13,800,000 devicesdevices hourshoursCMC: 141 FIT/Mb, from 101 to 193FIT/Mb@ 95% confidence intervalBRAM: 704 FIT/Mb, from 515 to 939FIT/Mb@ 95% confidence interval


The Rosetta (SEU) StoneThe Rosetta (SEU) StoneProcess FPGA

Lithography Family Cfg MC BRAM Cfg MC BRAM (1)cm2 cm2 FIT/Mb FIT/Mb

220nm Virtex 0.99E-14 0.99E-14 157 157180nm Virtex-E 1.12E-14 1.12E-14 177 177150nm V2 2.56E-14 2.64E-14 396 431130nm V2P 2.74E-14 3.91E-14 375 60890nm S3 2.40E-14 3.48E-14 190 37390nm V4 1.55E-14 2.74E-14 240 38090nm S3E/A 1.31E-14 2.73E-14 104 29365nm V5 0.67E-14 3.96E-14 138 701

LANSCE >10MeV ROSETTA

Notes:CalculationsCalculations accordingaccording JESD89A JESD89A ValidValid for NYC: 40.7for NYC: 40.7N N latlat, 286.0, 286.0 long, long, SeaSea--levellevel, Neutron flux= 1.000, Neutron flux= 1.000(1) Error estimates for each Rosetta measurement @ 95% confidence interval:

o 90nm S3 [-50,+80]%, 90nm S3E [-80, 90]%o 250nm +/-20%, 180nm +/-20%, 150nm V2 +/-8.2%, 130nm V2P +/-11.1%, 90nm V4 +/-17.7%, 65nm V5 [-27, +34]%

(2) Not enough Rosetta Gbit-years for useful prediction accuracy at this point (experiment running), predicted from LANSCE(3) All data as of 26aug08*Config FIT/Mb *Config FIT/Mb doesdoes not not includeinclude SEUPI= 10SEUPI= 10 (no de-rating factor). Divide configuration FIT/Mb by ten to get 1-sigma worst case

(most pessimistic) de-rating factor.





Summary


RTCA DORTCA DO--254 / EUROCAE ED254 / EUROCAE ED--8080

Product of RTCA SCProduct of RTCA SC--180 and EUROCAE WG180 and EUROCAE WG--4646 RTCA: Requirements and Technical Concepts for Aviation EUROCAE: EURopean Organisation for Civil Aviation Equipment

Title:Title:Design Assurance Guidance for Airborne Electronic HardwareDesign Assurance Guidance for Airborne Electronic Hardware (AEH)(AEH) For PLDs, FPGAs and ASICs A design flow with checkpoints, verification and expert review Certification pronounced by

Designated Engineering Representative (DER) in NA, representing FAA, EASA (European Aviation Safety Agency), directly in Europe.

Represents a consensus of best practices for aviation

DODO--254254


DODO--254 Section 3254 Section 3HW Design Life CycleHW Design Life Cycle

A-Planningprocess

(section 4)

- 1 -Requirements

Capture(section 5.1)

- 2 -Conceptual

Design(section 5.2)

- 3 -DetailedDesign

(section 5.3)

- 5 -ProductionTransition

(section 5.5)

- 4 -Implementation

(section 5.4)

C- Correctness Process Validation & Verification process (section 6) Configuration Management (section 7) Process Assurance (section 8) Certification Liaison (section 9)

B- Development Process

Derived Requirements

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3 Key Processes / 5 Design phases(A-B-C) (1-2-3-4-5)

DODO--254254


SiliconDownload Bitstreaminto FPGA device

Download Bitstreaminto FPGA device

Place & RoutePlace & Route

RTL DesignRTL Design

ConceptualDesign

ConceptualDesign

RequirementsCapture

RequirementsCapture

PlanningPlanning

SynthesisSynthesis

Detailed Design

DODO--254 FPGA Design flow254 FPGA Design flowProject Plans: PHAC, Project Plans: PHAC, PA/QA plan, CM plan, PA/QA plan, CM plan, DevDev. plan, Ver. plan . plan, Ver. plan

System System RequirementsRequirements System Safety Analysis System architecture SW & HW allocation

HW HW requirementsrequirements: : Feasible, Verifiable

HW Design: HW Design: RTL design, Synthesis, P&R HW TestHW Test

Functional tests Normal range tests Robustness tests:

Power supplies,TC, Vibrations & shocks, Radiations

Coverage analysis TracaebilityTracaebility: : Correlation between reqs, design, implementation and verification.

HAS: HAS: Identify & Justify Deviations vs PHAC.

MapingMaping

TranslateTranslate

Implementation

DesignValidation & Verification

Verify RTL DesignVerify RTL Design

Verify Gate-Level Design

Verify Gate-Level Design

Debug

Works OK? YES / NO => Back to HDL Design

DeviceDevice LevelLevel

System System LevelLevelWorks OK? YES / NO => Investigate

DODO--254254

Design Review

VerificationReview

RequirementsReview


XilinxXilinx DODO--254 254 partnershippartnership

Training and consulting partnerships

Tools for a requirements-driven design methodology ReqTracer HDL Designer* ModelSim SE 0-In CDC* Precision,

HW packages and business models geared for the aviation market

* Customized for a Xilinx Flow


OUTLINEOUTLINE Xilinx introduction Products overview Aerospace & Defense introduction Avionics solutions


Space solutionsSpace solutions Product offering Space Environment Testing & Results Mitigations techniques XTMR architecture & TMRtool

Summary


Challenges for Designing Challenges for Designing Space ApplicationsSpace Applications

Becoming increasingly sophisticated High data rates and packet processing

ASICs are capable of high performance, but Long development times, re-spin risk, and NRE are problems Space unit volumes are better addressed by FPGAs

Previous FPGA solutions Not capable of high-performance applications Not reprogrammable No built-in processing or I/O capabilities

Designers Need High-Performance FPGAs Capable of Embedded and Signal Processing in Space


SingleSingle--Chip Solution Addresses Chip Solution Addresses Performance RequirementsPerformance Requirements

High-performance applications Video (compression, encode, decode) Communications (filtering, processing) Radar (filtering, processing) Encryption (AES, 3DES, proprietary) Packet Processing (802.3, web server)

Control applications Motor control (low and high-performance) Bus management (Ethernet, Fiber channel, etc.)

High-performance applications Video (compression, encode, decode) Communications (filtering, processing) Radar (filtering, processing) Encryption (AES, 3DES, proprietary) Packet Processing (802.3, web server)

Control applications Motor control (low and high-performance) Bus management (Ethernet, Fiber channel, etc.)


Selected advanced FPGA products for application in Space-based systems Complete Single Event Effects testing and analysis

Tools and techniques for SEU mitigation & management Applications solutions

Configuration Management & Scrubbing Special architectural feature considerations Embedded Processing Reference Designs

TMRTool Software Automated Triple Module Redundancy implementation tool

Xilinx Solutions for SpaceXilinx Solutions for SpaceHighest Performance, Largest Capacity FPGAs in Space


Guaranteed Quality for SpaceGuaranteed Quality for Space

Guaranteed TID of 300 krad (Si)

Full Military Temperature Range (-55C to +125C)

SEL Immunity >125

MeVcm2/mg

True Class-VFlows

Radiation-hardened military ceramic package (QML in process)

Aerospace Corporation Certification


Xilinx QPro Aerospace Products

Aerospace QPro-R Radiation Tolerant Configuration PROMsSEL Immunity

Device Core Storage Bits Mfg Grades Packages TID (krad) (MeV-cm^2/mg)

QPro-R PROMs XQR1701L 3.3V 1M M, V CC44 50 >120

XQR17V16 3.3V 16M M, V CC44, VQ44 50 >120

Aerospace QPro-R Radiation Tolerant FPGAsSEL Immunity

Device Core Mfg Grades Packages TID (krad) (MeV-cm^2/mg) QPro-R Virtex-IV XQR4VLX200 1.2V V CF1509 300 >80

XQR4VSX55 1.2V V CF1140 300 >80XQR4VFX140 1.2V V CF1144 300 >80XQR4VFX60 1.2V V CF1509 300 >80

QPro-R Virtex-I I XQR2V3000 1.5V M, V BG728, CG717 200 >160XQR2V6000 1.5V H CF1144 200 >160

QPro-R Virtex XQVR300 2.5V M, V CB228 100 125XQVR600 2.5V M, V CB228 100 125

Enhanced Rad Hard by Design products in development


Space Products Roadmap Space Products Roadmap

2004 2008 2010

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XQR4VSX55XQR4VFX60XQR4VFX140XQR4VLX200

300KRad

XQR2V3000XQR2V6000

200KRad

SIRFXQRS5VFX130T

>300KRad

Rad Tolerant FPGAs

Rad Tolerant FPGAs

Rad Hard by Design FPGAs


Xilinx Virtex-4QV

Multi-platform FPGA family with embedded hard IPHigh-performance logic platformEmbedded / Ethernet MACs platformDSP optimized platform

Unmatched capacity and system integration Radiation tolerant devices meet Class-V requirements Reprogrammable technology enables changes at any time

XQR4VSX55 XQR4VFX60 XQR4VFX140 XQR4VLX200

Logic Cells 55,296 56,880 142,128 200,448CLB Flip-Flops 49,152 50,560 126,336 178,176

Distributed RAM (Kbits) 384 395 987 1392

XQR4VSX55 XQR4VFX60 XQR4VFX140 XQR4VLX200

Logic Cells 55,296 56,880 142,128 200,448CLB Flip-Flops 49,152 50,560 126,336 178,176

Distributed RAM (Kbits) 384 395 987 1392

New in 2008!


U.S. Government Agency ControlsU.S. Government Agency Controls

US DepUS Dept. of Commerce t. of Commerce Bureau of Industry & Security

Export Administration Regulations Export Administration Regulations Dual Use products/ technologiesCommerce Control List

US Department of State US Department of State Directorate of Defense Trade Controls

International Traffic in Arms Regulations Inherently military products/ technologiesU.S. Munitions List

US Department of TreasuryUS Department of TreasuryOffice of Foreign Assets Controls

Administration of US economic sanctions & embargoes

Xilinx Virtex-4QV are under US DoC EARAdministered by Bureau of Industry and Security (BIS)


SIRF(Single-Event Immune Reconfigurable FPGA)

Key Development Objectives Deliver Radiation Hardened by Design, Space qualified Virtex-5

FPGA by CY2010 Minimize design complexities and overhead required Space

applications of FPGAs Eliminate additional design effort and chips for configuration management,

scrubbing, TMR and state recovery Maintain compatibility with commercial V-5 product for rapid

development Feature set, floor plan and footprint compatible with commercial product

Address critical SEE sensitive circuits and eliminate all SEFIs Transparent to S/W Development Tools


SIRF Phases 3 & 4

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WERPC

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WERPC

FX-1 SEE Hardening Configuration Memory Configuration Controller CLB IOB BRAM Configuration

FX-1 SEE Hardening Configuration Memory Configuration Controller CLB IOB BRAM Configuration

Comprehensive Testing Speed Characterization Static and Dynamic SEE Total Dose Dose Rate

Comprehensive Testing Speed Characterization Static and Dynamic SEE Total Dose Dose Rate

FX-2 SEE Design Hardening Determine performance and

mitigation strategies Implement feasible enhancement

to DSP, BRAM, CMT, PPC and MGT as require

FX-2 SEE Design Hardening Determine performance and

mitigation strategies Implement feasible enhancement

to DSP, BRAM, CMT, PPC and MGT as require


SIRF Radiation Goals & DeviceSIRF Radiation Goals & Device

Total Dose > 300 krad (Si) (requirement)

Dose Rate Latch up > 1 10 10 rad(Si)/secUpset > 1 10 9 rad(Si)/sec

SEELatch up Immune LET > 100 MeV-cm2/mg

Upset Error rate < 1 10-10 errors/bit-day

FunctionalInterrupt

Error rate < 110 errors/bit-day-102PPC440 Cores

20RocketIO GTX Channels

84042.5FF1738

SizePackage

610/100/1000 EMACs

3PCIe Subsystem Blocks

0RocketIO GTP Channels

301DSP48E Slices

10,836Total Block RAM (Kbits)

131,072Logic Cells

FX130T


U.S. Government Agency ControlsU.S. Government Agency Controls

US DepUS Dept. of Commerce t. of Commerce Bureau of Industry & Security

Export Administration RegulationsDual Use products/ technologiesCommerce Control List

US Department of State US Department of State Directorate of Defense Trade Controls

International Traffic in Arms Regulations International Traffic in Arms Regulations Inherently military products/ technologiesU.S. Munitions List

US Department of TreasuryUS Department of TreasuryOffice of Foreign Assets Controls

Administration of US economic sanctions & embargoes

Xilinx SIRF will be US DoD ITAR

Xilinx Confidential

TEST MethodologySpecification Control Xilinx Data SheetMask Control Per XILINX Controlled Doc.QML Qualified WaferFab Per Mil - PRF 38535Wafer Lot Acceptance Per Internal Parametric SpeciLot RHA Per TM1019 / Per WaferFab Lo QML Qualified Assembly Per Mil - PRF 38535Destructive Bond Pull Per TM2011, Sample, SPCInternal Visual Per TM2010B, 100%Temperature Cycling Per TM1010, 100%Constant Acceleration Per TM2001, 100%Fine/Gross leakage Per TM1014, 100%Pind-Test Per TM2020Radiography Insp / X-Ray Per TM2012, Sample, SPC Pre-BI Test @ 25C Per SMD or DataSheetStatic Burn-in (240 hours) Per TM1015B, 100%Post BI Test @ 25C Per SMD or DataSheetPDA Calculation Per TM5004+125C Electrical Test Per SMD or DataSheet-55C Electrical Test Per SMD or DataSheetMarking Permanency Per TM2015DPA Per TM1580QC Sampling Plan Per TM5005, Group A (0/116)QCI Per TM5005, Groups B, C & D External Visual Inspection Per TM2009, 100%

XX Com. Std Com. Std

XX X X

XX X X

XX X X

XXXX

XX XX

X Sample SampleX X

X X XX X X

X X XX

X X XX X X

QPRO V-Grade Ceramic M-Grade Ceramic M-Grade PlasticX X X

QA flowsQA flows


Xilinx Spaceflight Heritage

50 new programs underway

MARS Lander (JPL) Pyrotechnics MARS Rover (JPL) Motor Control MRO (Ball Aerospace) HiRISE Camera GRACE (NASA) Sensor Venus Express (ESA) Multiple Virtex designs FedSat (Univ. Southern Australia) OPTUS (Raytheon) - DSP TACSAT2 (NASA) CIBOLA (LANL) Remote Sensing National Nuclear Security Administration's

reconfigurable supercomputing payload




Space solutionsSpace solutions Product offering Space Environment Testing & Results Mitigations techniques XTMR architecture & TMRtool

Summary


Xilinx Radiation Test ConsortiumXilinx Radiation Test Consortium

Founding partner of Radiation Test Consortium

SEE testing and qualification with Space industry leaders JPL, Sandia National Laboratories, Aerospace Inc.,

NASA Goddard, Los Alamos National Laboratories, SEAKR, Boeing, Northrop Grumman, General Dynamics, Lockheed Martin, IBSI, and many others

European SEE consortium: To restart soon.

Static and Dynamic SEE and TID testing Full validation of SEU mitigation methods Results published in peer-reviewed journals


Mature Test Methods & ApparatusMature Test Methods & Apparatus


QproQpro--R R VirtexVirtex--IIIIWeibullWeibull Curve SummaryCurve Summary

CELL/SEFI CELLS PER DEVICE ONSET POWER WIDTH LIMIT2V1000 2V3000 2V6000 MeV-cm2/mg(MeV) - - Cm

2

Heavy Ion(Proton)

CONFIG 2787740 7347524 16395508 1.0(3.0)

0.8(0.5)

33(12)

4.37E-8(3.8E-14)

BRAM 737280 1769472 2654208 1.0(3.0)

0.9(0.6)

17(12)

4.19E-8(4.1E-14)

POR1 1 1 1 1.5(7.0)

1.2(1.0)

22(12)

2.50E-6(3.74E-13)

SMAP2 1 1 1 1.5(6.5)

1.0(0.5)

17(12)

1.72E-6(5.72E-13)

JCFG3 1 1 1 1.5(6.0)

1.0(0.5)

17(12)

2.51E-7(2.86E-13)

1. Single Event Functional Interrupt clears configuration memory.2. Single Event Functional Interrupt deactivates configuration memory read/write access from SelectMAP Port.3. Single Event Functional Interrupt deactivates configuration memory read/write access from JTAG Port.


QproQpro--R R VirtexVirtex--II Orbital RatesII Orbital RatesConfiguration Memory Cells

Upsets/Device-Day

Typical Solar Conditions

Orbit LEO LEO POLAR CONST. GEO

Altitude (km) 400 800 833 1,200 36,000

Inclination 51.6 22.0 98.7 65.0 0

XQR2V3000 0.30 4.0 2.7 11.0 0.21

XQR2V6000 0.67 9.0 6.0 25.0 0.47

Functional Interrupts (All Virtex-II)Upsets/Device-Day


POR + SMAP + JCFG 2.33E-06 9.87E-06 5.44E-06 2.74E-05 2.00E-06

Device-Years/Event

All SEFIs (Combined) 2,185 277 503 100 1,369

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VirtexVirtex--4 Static SEU Plots4 Static SEU Plots

10-10

10-9

10-8

10-7

0 20 40 60 80 100 120Effective LET (MeV*cm2/mg)

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SX55FX60LX200

POR SEFI

10-13

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10-16

0 20 40 60 80 100 120Energy (MeV)

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10-14

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0 20 40 60 80 100 120Energy (MeV)

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SX55FX60LX200

POR SEFI


VirtexVirtex--4QV Orbital Rates4QV Orbital RatesConfiguration Memory Cells

Upsets/Device-Day


Orbit LEO LEO POLAR CONST. GEO

Altitude (km) 400 800 833 1,200 36,000

Inclination 51.6 22.0 98.7 65.0 0

XQR4VSX55 0.76 7.43 5.12 20.0 4.20

XQR4VFX60 0.80 7.79 5.36 20.9 4.40

XQR4VFX140 - - - - -

XQR4VLX200 2.15 21.0 14.5 56.5 11.9

10313.35336412All SEFIs (Combined) Device-Years/Event

4.87E-066.47E-051.57E-052.41E-051.57E-06GSIG

9.46E-066.71E-051.69E-052.45E-052.25E-06SMAP+FAR

1.21E-057.36E-051.85E-052.73E-052.83E-06POR


Upsets/Device-Day

Functional Interrupts (All Virtex-4)

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Space solutionsSpace solutions Product offering Space Environment Testing & Results Mitigations techniquesMitigations techniques XTMR architecture & TMRtool

Summary


Mitigating Mitigating SEEsSEEs

We cant PREVENT SEUs and SETs

We can only MITIGATE their effects


Mitigation SchemesMitigation Schemes


No MitigationNo Mitigation

Also known as Power Cycle Clear all issues May not be applicable


ScrubbingScrubbingAlso Known as configuration management

Process of correcting configuration upsets through partial reconfiguration Doesnt alter FD value SRL16/LUTRAM a problem until V4 and later BRAM

Complete solution includes SEFI detection and correctionHosted externally or internally


Traditional Traditional ConfigConfig Management SetupManagement Setup


Single FPGA Self Scrubbing SetupSingle FPGA Self Scrubbing Setup

Virtex (II) Series

DATA (0:7)BUSYINITDONECCLKPROGRDWRCS

XQR18V04/17V16DATA (0:7)

BUSY*OE/RESET

CECLK

WATCH DOG*17v16 only

FPGAPROM

IO(0:7)(2:0)IO (2:0)IO (2:0)IO (2:0)IO (2:0)

IO (2:0)

OSC

IO (2:0)

Master SelectMAP PROM Boot with Internal Scrub Controller

IO (2:0)IO (2:0)IO (2:0)

Reset

SEFIPULSE


XTMRXTMR

Automate triplication of designAutomate triplication of designVoter insertion Auto resync for any FD with feedback

path. (ie. Counter, FSM)Primitive level triplicationHalf Latch, SRL16 extractionCustom Macro for primitives/design modules too complicated for simple triplication

DCM, BRAM, bi-directional IO

MAJORITYVOTER

MAJORITYVOTER

MAJORITYVOTER


Redundant DevicesRedundant Devices

Multiple FPGAs usedMultiple FPGAs used2, 3, 4+ FPGA schemes 4+ scheme: 3 as primary, others as

backupMost robust mitigationResync Coding more challenging May not be feasible for all designs


Mitigation SurveyMitigation SurveyCost and Benefit tableCost and Benefit table




Space solutionsSpace solutions Product offering Space Environment Testing & Results Mitigations techniquesMitigations techniques XTMR architecture & TMRtool

Summary


XTMR architectureXTMR architecture

AFTER

AB

CLK X

COMBLOGIC

COMBLOGIC

COMBLOGIC

MAJORIYVOTER

MAJORIYVOTER

MAJORITYVOTER

MINORITYVOTER

MINORITY VOTER

MINORITY VOTER

COMBLOGIC

AB

CLK

XBEFORE


TMRToolTMRTool Result of Xilinx/Sandia National Labs partnership

An Application that will automatically implement TMR techniques on a user design

Allows user to implement custom TMR logic Support all design entry methods and HLLs

NGO & NGC based input EDIF based output

OS Support Windows 2000/XP GUI Support Windows/UNIX PERL Command Line Support Linux TBD

Supports ISE 9.2i, will support ISE10.1i by Q1CY09 Production Release : Now (TMRtool10.1i available by Feb09)


Design FlowDesign Flow

It is recommended to run Step1 up to the design validation and come back to Step2 of TMRtool design flow

MAP

PAR

BitGen




Space solutions Product offering Space Environment Testing & Results Mitigations techniquesMitigations techniques XTMR architecture & TMRtool

SummarySummary


SummarySummary

Leading commercial technology has been leveraged for the Aerospace and Defense Industries: Density, performance, and reconfigurability Established Military/High Reliability manufacturing flows

Comprehensive SEE Characterization: Static SEU characterization of all internal storage and control cells Dynamic functional & transient response and SEFI/error mechanisms

quantified/characterized Full public disclosure of all test results through the SEE Consortium

Mitigation methods evaluated, demonstrated, and verified RadHard by Design program initiated

Increase hardness levels and eliminate SEFI modes and the requirements for TMR Techniques developed for the Space community synergistic with Avionics and

Terrestrial requirements for future technologies

Xilinx Confidential

XILINX Aerospace solutionsOUTLINEXilinx FactsInnovation at XilinxDigital Convergence Drives DemandXilinx Serves a Wide Range of MarketsOUTLINEProgrammable MethodologyAbstracting Away the HardwareISE Design Suite 10.1 1 Environment for Logic, Embedded and DSP DesignIntellectual Property CoresAugment Your Own R&D to Maximize Productivity and Reduce risk Products SolutionsOUTLINEXilinx Continuous CommitmentXilinx in Aerospace & DefenseGrowth Focused on TransformationXilinx Aerospace & Defense Integration SolutionsOUTLINESpartan-3 familyOptimized Platforms Save CostVirtex-5 FPGA FamilyThe Ultimate System Integration PlatformXilinx FPGA roadmapOUTLINETerrestrial SEE testing methodologyLow Noise Underground TestingOCA-LSBB Reference levelAltitude testingOMP + CMB sitesThe Rosetta (SEU) StoneOUTLINERTCA DO-254 / EUROCAE ED-80DO-254 Section 3HW Design Life CycleDO-254 FPGA Design flowXilinx DO-254 partnershipOUTLINEChallenges for Designing Space ApplicationsSingle-Chip Solution Addresses Performance RequirementsXilinx Solutions for SpaceHighest Performance, Largest Capacity FPGAs in SpaceGuaranteed Quality for SpaceXilinx QPro Aerospace ProductsSpace Products Roadmap Xilinx Virtex-4QVU.S. Government Agency ControlsSIRF(Single-Event Immune Reconfigurable FPGA)SIRF Phases 3 & 4SIRF Radiation Goals & DeviceU.S. Government Agency ControlsXilinx Spaceflight HeritageOUTLINEMature Test Methods & ApparatusQpro-R Virtex-IIWeibull Curve SummaryQpro-R Virtex-II Orbital RatesVirtex-4 Static SEU PlotsVirtex-4QV Orbital RatesOUTLINEMitigating SEEsMitigation SchemesNo MitigationScrubbingTraditional Config Management SetupSingle FPGA Self Scrubbing SetupXTMRRedundant DevicesMitigation SurveyCost and Benefit tableOUTLINEXTMR architectureTMRToolOUTLINESummary

04 silica xilinx

Documents

xilinxcnes cct fpgajlm

nm fpgas

nm virtex

marketxilinx confidential2008

fpgasxilinx confidential2008

nm expressfabric technology

nm production fpgas

programmable solutions