0.13-um sige bicmos radio front-end circuits for 24-ghz automotive short-range radar sensors

8/10/2019 0.13-Um SiGe BiCMOS Radio Front-End Circuits for 24-GHz Automotive Short-Range Radar Sensors

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The circuit consists of three gain stages, which exploit afully differential topology to avoid detrimental effects of

parasitic ground inductance and to provide high rejection ofcommon-mode spurious signals and substrate noise. Eachamplifier stage adopts a transformer-loaded cascode topology,which allows first-rate reverse isolation, excellent power gain,

and high linearity to be achieved. The first stage, LNA1, wasdesigned to achieve simultaneous noise/input impedancematching by using optimum transistor sizing and emitterinductors (LE1). On the contrary, in both LNA2 and LNA3inductive emitter degeneration (LE2, LE3) was employed totrade-off power gain and linearity performance. Transformerresonant loads (TL1, TL2, and TL3) were accurately designed tooptimize the overall power gain performance by maximizingthe transformer characteristic resistance (TCR) [3]. The designof an integrated transformer is an issue of great concern atmm-wave frequencies since the adopted inductance values fallin the sub-nH range [4]. Moreover, the TCR optimization

procedure requires iterative steps and time consumingelectromagnetic (EM) simulations. For these reasons, scalablelumped model was first exploited to define the spiralgeometrical parameters, and then a 2D EM simulator (AgilentMomentum) was used to validate the transformer layoutstructure and refine its EM behavior, taking into account theconnection paths. Finally, to guarantee the required gain

bandwidth flatness, which is an issue of great concern in multistage amplifiers with resonant load, the inter-matching LCnetworks were properly designed.

A variable-gain approach is also adopted to relax linearityrequirements of the I-Qmixers and subsequent blocks in thereceiver chain. As shown in Fig. 1, a single-bit gain control isachieved by means of the control voltage, VCTRL. In particular,at low-gain setting (VCTRL= 2.5 V) the current delivered to the

resonant load depends on the emitter area ratio of transistorsQ8,9, Q11,12 (Q16,17, Q19,20), while at high-gain setting(VCTRL= 0 V) the stages work as traditional cascodeamplifiers. This technique significantly increases the receiverlinearity, still maintaining excellent noise figure performance.At the output, differential-to-single-ended conversion isinherently provided by the transformer TL3, while at the inputan integrated balun (Tin) was included for testing purpose.

The layout drawing of mm-wave Si-based blocks is acrucial phase in the overall design flow. Indeed, geometricalasymmetries, interconnection path parasites, and EM coupling

produce considerable degradation of the expected results.Moreover, a poor on-chip ground reference, due to the

stringent metal density rules of modern processes furtherdeteriorates both circuit reliability and performance. For thesereasons, much attention was paid to the design of differentialsignal paths in terms of symmetry and length. This was alsoaccomplished by adopting a symmetric interleaved structurefor the transformer loads TLand differential folded microstripsto implement degeneration inductors LE. Furthermore, alow-resistance/low-inductance ground plane was adopted,which makes use of an appropriate metal 2/metal 3 pattern tomeet density requirements still implementing a well-definedon-chip ground reference for the LNA. Finally, extensive EM

post-layout simulations were carried out to take into accountRLCparasitics and coupling effects.

B. 24-GHz Synthesizer

The design of a frequency synthesizer working atoperating frequency higher than 5 GHz is an issue of greatconcern. The design of both low-noise oscillator andhigh-frequency prescaler represents the bottleneck todemonstrate the feasibility of Si-based chips for

high-frequency applications. This work uses a 24-GHz PLL,adopting a well-established architecture composed of

phase/frequency detector (PFD), charge pump, external loopfilter, voltage-controlled oscillator (VCO), and N-integerdivider. Using a division ratioNof 2048 a 24.125-GHz carrieris achieved with a PLL reference frequency fREF of11.78 MHz. A second order loop filter is used to set PLL

bandwidth at 200 kHz.

The VCO, whose simplified schematic is depicted Fig. 2,uses a bipolar core with high-QLC resonator. An issue ofgreat concern is the design of both capacitors and inductor inthe LC tank. This resonator exploits accumulation MOS(A-MOS) variable capacitors and a single-turn inductor whose

value at 24 GHz is as low as 230 pH. As reported in [4], bothmeasurements and modeling of such sub-nH spirals are quitecritical. To overcome these problems and take into account allconnection paths, EM simulators are extensively adoptedduring the resonator design.

Finally, theN-integer divider is designed using a chain of11 divider-by-two stages. Each stage uses flip-flop inclosed-loop master-slave configuration. High-speed flip-flopsare designed using current-mode-logicD-latches. Each dividerdrives the subsequent one using an emitter follower stage. Thedesign of high-speed D-latches requires accurate RLCextraction and evaluation of connection paths during layoutdrawing. To this aim, in addition to conventional post layout

flows, commercial EM simulator was largely exploited toguarantee working capabilities beyond 30 GHz.

C. UWB Transmitter

The modulated pulses are generated by using a sub-nsswitch, whose simplified schematic is shown in Fig. 3. Acurrent steering approach is adopted. The 24-GHz signaldrives the RF port, while the pulse signal coming from the

pulse generator (PG) steers the RF signal into the output portto generate the 24-GHz modulated pulse. The switch is

properly designed to deliver a 0-dBm output power complyingwith 1-ns pulse transmission requirements, thus avoiding theneed of an additional amplifier. A resonant load composed of

MIM capacitor, CL, and stacked transformer, TLOAD, isadopted. The design of the output transformer TLOAD is anissue of great concern. First a simplified lumped model [5]was exploited to define the transformer geometrical

parameters and then a commercial 3D EM simulator, AnsoftHFSS, was used to simulate the layout structure, taking intoaccount all the connection paths. The monolithic transformer

provides both differential-to-single-ended conversion of theoutput signal and ESD protection, as well. Thanks to thesecondary inductor of TLOAD, the current generated byelectrostatic discharge is shorted to the ground without anyESD protection diode loading the RF stage.

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Figure 2. Simplified schematic of the VCO and buffer.

Figure 3. Simplified schematic of TX output switch.

III. EXPERIMENTAL RESULTS

A 0.13-m SiGe:C BiCMOS technology featuringhigh-speed npn transistors with fT/fmaxof 166/175 GHz, dualVTdual gate oxide CMOS devices, high-quality passives and6-level metal copper back-end was used [6]. For testing

purpose, the chips were mounted on a 400-m thick FR4substrate adopting chip-on-board assembly technique.

The die photograph of the LNA is shown in Fig. 4. TheLNA measurement setup consists of a two-port HP8510vector network analyzer, a Summit 12000 Cascade Microtech

prober, and an Agilent N8975A noise figure analyzer. Testingwas carried out at 2.5-V supply voltage. Raw data werede-embedded only for the input stacked balun loss. The powergain and noise figure at high-gain setting are reported inFig. 5. The amplifier achieves a maximum gain of 35 dB and a3.4-dB noise figure. At low-gain setting the LNA provides a14.5-dB power gain, while exhibiting a noise figure of 4.5 dB.Thanks to the gain-control functionality, the circuit achieves a1-dB compression point (P1dB) of 12 dBm. Both input andoutput return losses are shown in Fig. 6. The LNA exhibits aS12better than 53 dB in the whole operative frequency range,thus demonstrating the effectiveness of the adopted isolationtechniques.

The die photograph of the overall UWB transmitter isshown in Fig. 7. The PLL was characterized usingAgilent 4440A spectrum analyzer, which features an operating

bandwidth as large as 26.5 GHz. The output spectrum

centered at 24.125 GHz carrier is shown in Fig. 8. The carrierpresents two tones at a frequency offset of 11.78 MHz (PLLreference frequencyfREF), whose levels are 50 dBc lower. Themeasured output power is about 4.65 dBm, whichcorresponds to a delivered power of 0.8 dBm considering acable loss of 3.8 dB at 24 GHz. The maximum power is

1.5 dBm measured at 24.9 GHz.

Figure 4. Die photograph of the 3-stage LNA.

Figure 5. Power gain (S21) and noise figure at high-gain setting

(VCTRL= 0 V,PIN= 30 dBm).

Figure 6. Input (S11) and output (S22) return losses.

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The VCO exhibits a tuning range of 4.7 GHz from 20.4 to25.1 GHz, when the fREF sweeps between 9.78 to 12.2 MHz.The measured phase noise is 104.3 dBc/Hz at 1-MHz offsetfrom the carrier at 24.125 GHz, as shown in Fig. 9. The VCOcore consumes 5.8 mA from a 2.5-V power supply.

Fig. 10 shows the measured spectrum of the UWBtransceiver with a pulse repetition frequency (PRF) fixed to10 MHz. The spectrum presents a main lobe centered at24.125 GHz with two nulls at 23.25 and 25.08 GHzrespectively, which indicate a pulse transmission with TPulseof1.1 ns. The spectrum presents two secondary lobes, whose

power spectral density is 10 dBc lower than the main lobe.The carrier at 24.125 GHz is visible as a single tone due to thecontinuous leakage, as well. Basically, TX leakage is limited

by the isolation of transistors Q10, Q11, Q12, Q13 in off state(see at Fig. 3).

Figure 7. UWB transmitter die photograph.

Figure 8. Frequency synthesizer output spectrum.

Figure 9. Phase-noise at 1-MHz offset from the 24.125-GHz carrier.

Figure 10. Output spectrum for 1-ns trasmitted pulse

(PRF = 10 MHz, RBW = 1 MHz).

ACKNOWLEDGMENT

The authors would like to thank Alessandro Castorina,STMicroelectronics, Catania, Italy, for his valuable assistancewith measurements.

REFERENCES

[1] First report and order, revision of part 15 of the commissions rulesregarding ultra wideband transmission systems, FCC, Washington,DC, ET Docket 98 153, 2002.

[2] ETSI EN 302 288-1: Electromagnetic compatibility and Radiospectrum Matters (ERM); Short Range Devices; Road Transport and

Traffic Telematics (RTTT); Short range radar equipment operating inthe 24 GHz range; Part 1: Technical requirements and methods ofmeasurement.

[3] F. Carrara, A. Italia, E. Ragonese, and G. Palmisano, Designmethodology for the optimization of transformer-loaded RF circuits,IEEE Trans. Circuits Syst. I, vol. 53, pp. 761 768, Apr. 2006.

[4] T. Biondi, A. Scuderi, E. Ragonese, and G. Palmisano, Sub-nHinductor modeling for RF IC design,IEEE Microwave Wireless Comp.Lett, vol. 15, pp. 922-924, Dec. 2005.

[5] T. Biondi, A. Scuderi, E. Ragonese, and G. Palmisano, Analysis andmodeling of layout scaling in silicon integrated stacked transformers,IEEE Trans. Microwave Theory Tech., pp. 2203-2210, Apr. 2006.

[6] M. Laurens et al., A 150 GHz fT/fmax 0.13 m SiGe:C BiCMOStechnology, in Proc. IEEE Bipolar/BiCMOS Circuits Technol.Meeting, Oct. 2003, pp. 199-202.

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0.13-um sige bicmos radio front-end circuits for 24-ghz automotive short-range radar sensors

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